Mesa (master): i965: Add perf debug for depth/stencil alignment workaround.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 0d6a722ec4df73595d4159e5b35c6fd61f847a6c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d6a722ec4df73595d4159e5b35c6fd61f847a6c

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Dec 18 13:45:14 2012 -0800

i965: Add perf debug for depth/stencil alignment workaround.

Fixing these rendering bugs has been implicated in performance
regressions (which may be unfixable), but at least knowing that it's
happening should help diagnose those regressions.

Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

---

 src/mesa/drivers/dri/i965/brw_misc_state.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index b0a1918..d7724e3 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -370,6 +370,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
       }
 
       if (rebase_depth) {
+         perf_debug("HW workaround: blitting depth level %d to a temporary "
+                    "to fix alignment (depth tile offset %d,%d)\n",
+                    depth_irb->mt_level, tile_x, tile_y);
+
          intel_renderbuffer_move_to_temp(intel, depth_irb);
          /* In the case of stencil_irb being the same packed depth/stencil
           * texture but not the same rb, make it point at our rebased mt, too.
@@ -427,6 +431,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
    }
 
    if (rebase_stencil) {
+      perf_debug("HW workaround: blitting stencil level %d to a temporary "
+                 "to fix alignment (stencil tile offset %d,%d)\n",
+                 stencil_irb->mt_level, stencil_tile_x, stencil_tile_y);
+
       intel_renderbuffer_move_to_temp(intel, stencil_irb);
       stencil_mt = get_stencil_miptree(stencil_irb);
 
@@ -443,6 +451,14 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
       } else if (depth_irb && !rebase_depth) {
          if (tile_x != stencil_tile_x ||
              tile_y != stencil_tile_y) {
+            perf_debug("HW workaround: blitting depth level %d to a temporary "
+                       "to match stencil level %d alignment (depth tile offset "
+                       "%d,%d, stencil offset %d,%d)\n",
+                       depth_irb->mt_level,
+                       stencil_irb->mt_level,
+                       tile_x, tile_y,
+                       stencil_tile_x, stencil_tile_y);
+
             intel_renderbuffer_move_to_temp(intel, depth_irb);
 
             tile_x = depth_irb->draw_x & tile_mask_x;