Mesa (master): gallivm: enable stores of integer types. (v2) + fix ARL

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 117a0e91afa4fae55df88de48a058c9b881c6b14
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=117a0e91afa4fae55df88de48a058c9b881c6b14

Author: Dave Airlie <airlied at redhat.com>
Date:   Mon Feb  6 15:37:56 2012 +0000

gallivm: enable stores of integer types. (v2) + fix ARL

Infer from the operand the type of value to store.
MOV is untyped but we use the float store path.

v2: make MOV use float store path.

I've had to squash merge the ARL fix to be stored
as an integer in here to avoid regressions in a number
of piglit tests.

>From now on ARL stores to an integer just like HW does.

Signed-off-by: Dave Airlie <airlied at redhat.com>

---

 src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c |   16 ++++++-
 src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c    |   54 ++++++++++++++++----
 2 files changed, 59 insertions(+), 11 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index f2caece..1390b2e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -806,6 +806,20 @@ add_emit_cpu(
                                    emit_data->args[0], emit_data->args[1]);
 }
 
+/* TGSI_OPCODE_ARL (CPU Only) */
+static void
+arl_emit_cpu(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   LLVMValueRef tmp;
+   tmp = lp_build_floor(&bld_base->base,
+			emit_data->args[0]);
+   emit_data->output[emit_data->chan] = LLVMBuildFPToSI(bld_base->base.gallivm->builder, tmp,
+							bld_base->uint_bld.vec_type, "");
+}
+
 /* TGSI_OPCODE_CEIL (CPU Only) */
 static void
 ceil_emit_cpu(
@@ -1151,7 +1165,7 @@ lp_set_default_actions_cpu(
    lp_set_default_actions(bld_base);
    bld_base->op_actions[TGSI_OPCODE_ABS].emit = abs_emit_cpu;
    bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit_cpu;
-   bld_base->op_actions[TGSI_OPCODE_ARL].emit = flr_emit_cpu;
+   bld_base->op_actions[TGSI_OPCODE_ARL].emit = arl_emit_cpu;
    bld_base->op_actions[TGSI_OPCODE_CEIL].emit = ceil_emit_cpu;
    bld_base->op_actions[TGSI_OPCODE_CND].emit = cnd_emit_cpu;
    bld_base->op_actions[TGSI_OPCODE_COS].emit = cos_emit_cpu;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 920fed2..0ae7790 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -502,11 +502,6 @@ get_indirect_index(struct lp_build_tgsi_soa_context *bld,
                         bld->addr[indirect_reg->Index][swizzle],
                         "load addr reg");
 
-   /* for indexing we want integers */
-   rel = LLVMBuildFPToSI(builder,
-                         rel,
-                         uint_bld->vec_type, "");
-
    index = lp_build_add(uint_bld, base, rel);
 
    max_index = lp_build_const_int_vec(bld->bld_base.base.gallivm,
@@ -855,7 +850,6 @@ emit_fetch_predicate(
    }
 }
 
-
 /**
  * Register store.
  */
@@ -875,8 +869,26 @@ emit_store_chan(
    struct lp_build_context *uint_bld = &bld_base->uint_bld;
    LLVMValueRef indirect_index = NULL;
    struct lp_build_context *bld_store;
+   enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
 
-   bld_store = &bld->bld_base.base;
+   switch (dtype) {
+   default:
+   case TGSI_TYPE_FLOAT:
+   case TGSI_TYPE_UNTYPED:
+      bld_store = &bld_base->base;
+      break;
+   case TGSI_TYPE_UNSIGNED:
+      bld_store = &bld_base->uint_bld;
+      break;
+   case TGSI_TYPE_SIGNED:
+      bld_store = &bld_base->int_bld;
+      break;
+   case TGSI_TYPE_DOUBLE:
+   case TGSI_TYPE_VOID:
+      assert(0);
+      bld_store = NULL;
+      break;
+   }
 
    switch( inst->Instruction.Saturate ) {
    case TGSI_SAT_NONE:
@@ -986,8 +998,30 @@ emit_store_chan(
                            &bld->exec_mask, pred);
       }
       else {
-         LLVMValueRef temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index,
-                                              chan_index);
+         LLVMValueRef temp_ptr;
+
+         switch (dtype) {
+         case TGSI_TYPE_UNSIGNED:
+         case TGSI_TYPE_SIGNED: {
+            LLVMTypeRef itype = LLVMVectorType(LLVMInt32TypeInContext(gallivm->context), 4);
+            LLVMTypeRef ivtype = LLVMPointerType(itype, 0);
+            LLVMValueRef tint_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index,
+                                                        chan_index);
+            LLVMValueRef temp_value_ptr;
+
+            temp_ptr = LLVMBuildBitCast(builder, tint_ptr, ivtype, "");
+            temp_value_ptr = LLVMBuildBitCast(builder, value, itype, "");
+            value = temp_value_ptr;
+            break;
+         }
+         default:
+         case TGSI_TYPE_FLOAT:
+         case TGSI_TYPE_UNTYPED:
+            temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index,
+                                           chan_index);
+            break;
+         }
+
          lp_exec_mask_store(&bld->exec_mask, bld_store, pred, value, temp_ptr);
       }
       break;
@@ -1345,7 +1379,7 @@ lp_emit_declaration_soa(
       case TGSI_FILE_ADDRESS:
          assert(idx < LP_MAX_TGSI_ADDRS);
          for (i = 0; i < TGSI_NUM_CHANNELS; i++)
-            bld->addr[idx][i] = lp_build_alloca(gallivm, vec_type, "addr");
+            bld->addr[idx][i] = lp_build_alloca(gallivm, bld_base->base.int_vec_type, "addr");
          break;
 
       case TGSI_FILE_PREDICATE: