Mesa (master): i965/vs: Use the sampler for VS pull constant loading on Ivybridge.

Kenneth Graunke kwg at kemper.freedesktop.org
Thu Jan 26 15:57:44 PST 2012


Module: Mesa
Branch: master
Commit: 259b65e2e7938de4aab323033cfe2b33369ddb07
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=259b65e2e7938de4aab323033cfe2b33369ddb07

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Jan 26 05:38:28 2012 -0800

i965/vs: Use the sampler for VS pull constant loading on Ivybridge.

Substantially increases performance in GLBenchmark PRO:
- 320x240   => 3.28x
- 1920x1080 => 1.47x
- 2560x1440 => 1.27x

The LD message ignores the sampler unit index and SAMPLER_STATE pointer,
instead relying on hard-wired default state.  Thus, there's no need to
worry about running out of sampler units or providing SAMPLER_STATE;
this small patch should be all that's required.

NOTE: This is a candidate for release branches.
      (It requires the preceding commit to compile.)

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index dbe4dd0..917c927 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -647,6 +647,23 @@ vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 					  struct brw_reg dst,
 					  struct brw_reg index)
 {
+   if (intel->gen == 7) {
+      gen6_resolve_implied_move(p, &index, inst->base_mrf);
+      brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
+      brw_set_dest(p, insn, dst);
+      brw_set_src0(p, insn, index);
+      brw_set_sampler_message(p, insn,
+                              SURF_INDEX_VERT_CONST_BUFFER,
+                              0, /* LD message ignores sampler unit */
+                              GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+                              1, /* rlen */
+                              1, /* mlen */
+                              false, /* no header */
+                              BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+                              0);
+      return;
+   }
+
    struct brw_reg header = brw_vec8_grf(0, 0);
 
    gen6_resolve_implied_move(p, &header, inst->base_mrf);



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