Mesa (master): 23 new commits

Fri Jul 27 17:10:56 UTC 2012

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fdd8df20e4a730f80bf4c331012d832bffd7072e
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Tue Jul 24 16:59:05 2012 +0000

    r600g: Emit dispatch state for compute directly to the cs
    
    We no longer rely on an evergreen_compute_resource for emitting dispatch
    state.
    
    Reviewed-by: Marek Olšák <maraeo at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc0b8a46289d0e6b10c542df0856d51a0aabf9b0
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Tue Jul 24 14:49:25 2012 +0000

    r600g: Initialize VGT_PRIMITIVE_TYPE in the start_cs_cmd atom
    
    The value of this register will always be DI_PT_POINTLIST for compute
    shaders.
    
    Reviewed-by: Marek Olšák <maraeo at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3b013049126fb44d65a0a67001b04acbe778613
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Tue Jul 24 14:23:12 2012 +0000

    r600g: Atomize compute shader state
    
    Reviewed-by: Marek Olšák <maraeo at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=54973910676951050092c096046b213f6a6944b5
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Tue Jul 24 17:33:19 2012 +0000

    r600g: Add helper functions for emitting compute SET_CONTEXT packets
    
    Reviewed-by: Marek Olšák <maraeo at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9ef27276f83b021221fb7e2c7397719e143709c
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:56:08 2012 -0400

    radeon/llvm: Add instruction defs for branches on SI

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Thu Jul 26 08:41:00 2012 -0400

    radeon/llvm: Fix VOPC and V_CNDMASK encoding

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4bdd09d4714ae51b9f5675f7f5c678d431061e8
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:46:35 2012 -0400

    radeon/llvm: Assert if we try to copy SCC reg

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd1f19a191c648e7c6fdaac3167e900e4fed4a6d
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:40:30 2012 -0400

    radeon/llvm: Add SI DAG optimizations for setcc, select_cc
    
    These are needed for correctly lowering branch instructions in some
    cases.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd5d4c50738b15c4885105ef4dcc89a1ea9e02fb
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:32:43 2012 -0400

    radeon/llvm: Add support for encoding SI branch instructions

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=50ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:30:32 2012 -0400

    radeon/llvm: Add special nodes for SALU operations on VCC
    
    The VCC register is tricky because the SALU views it as 64-bit, but the
    VALU views it as 1-bit.  In order to deal with this we've added some
    special bitcast and binary operations to help convert from the 64-bit
    SALU view to the 1-bit VALU view and vice versa.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c424975572af2edd46863e5bb9fe3c51c96b4f9b
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:27:50 2012 -0400

    radeon/llvm: Add i1 registers for SI.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdda1cb914a291f42cb2221b42e922f22dccb777
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:33:34 2012 -0400

    radeon/llvm: Fix CCReg definitions on SI

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae9be358f2d1e177648fb1803f152ff0b0bb9893
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:22:30 2012 -0400

    radeonsi: Enable PIPE_SHADER_CAP_INTEGERS

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=022b54359a0c8cc0a219b19b1f381cce66b35d35
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:23:52 2012 -0400

    radeonsi: Add support for loading integers from constant memory

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad95bcb31fcf49015446f5158dfaf97fefac75cd
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Thu Jul 19 13:29:15 2012 -0400

    radeon/llvm: Add bitconvert patterns for SI

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cab682184640242d1e6f034f2b6bd7c4378c162
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Thu Jul 19 13:28:25 2012 -0400

    radeon/llvm: Add custom lowering for SELECT_CC nodes on SI

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba76684292e568c164cb7cbe7537181af4b452b8
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Thu Jul 19 13:26:41 2012 -0400

    radeon/llvm: Move conditional pattern leafs to common tablegen file

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d36455ba2c3febe5da6fc6f53e4acd98f771532a
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 25 08:41:29 2012 -0400

    radeon/llvm: Implement getSetCCResultType for SI

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 18 13:39:00 2012 -0400

    radeon/llvm: Custom lower BR_CC for SI

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=87272e9e2560a88352cf54d164507569ac43e502
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 18 12:47:11 2012 -0400

    radeon/llvm: Move lowering of BR_CC node to R600ISelLowering
    
    SI will handle BR_CC different from R600, so we need to move it
    out of the shared instruction selector.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=92823fb72abf1539bdb545fedc5525e9fc0b04cc
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 18 12:26:45 2012 -0400

    radeon/llvm: Move lowering of SETCC node to R600ISelLowering
    
    SI will handle SETCC different from R600, so we need to move it
    out of the shared instruction selector.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=46d12c99a24cebe01cd00575b39961231dec47c8
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 18 12:22:33 2012 -0400

    radeon/llvm: Use correct node type when lowering SETCC

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=47d1b0a80990dda4e14073f667f0c2b939dfb925
Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed Jul 18 11:59:14 2012 -0400

    radeon/llvm: Move LowerSELECT_CC into R600ISelLowering
    
    SI will handle SELECT_CC different from R600, so we need to move it out
    of the shared instruction selector.