Mesa (master): radeon/llvm: Remove AMDIL VCREATE* instructions
Tom Stellard
tstellar at kemper.freedesktop.org
Wed Jun 6 13:50:19 UTC 2012
Module: Mesa
Branch: master
Commit: de7366701d21842787d65320c12e6b4ecaea3807
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de7366701d21842787d65320c12e6b4ecaea3807
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Sat Jun 2 07:09:16 2012 -0400
radeon/llvm: Remove AMDIL VCREATE* instructions
This obsoletes the AMDGPULowerInstruction pass.
---
src/gallium/drivers/radeon/AMDGPU.h | 1 -
src/gallium/drivers/radeon/AMDGPUInstructions.td | 6 ++
.../drivers/radeon/AMDGPULowerInstructions.cpp | 88 --------------------
src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp | 1 -
src/gallium/drivers/radeon/AMDILInstructions.td | 6 --
src/gallium/drivers/radeon/Makefile.sources | 1 -
src/gallium/drivers/radeon/R600Instructions.td | 3 +
src/gallium/drivers/radeon/SIInstructions.td | 3 +
8 files changed, 12 insertions(+), 97 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h
index 9d81bc2..191f495 100644
--- a/src/gallium/drivers/radeon/AMDGPU.h
+++ b/src/gallium/drivers/radeon/AMDGPU.h
@@ -28,7 +28,6 @@ FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
// Passes common to R600 and SI
-FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm);
FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
} // End namespace llvm
diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index 28ea93d..9ec9c4d 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -104,6 +104,12 @@ class Insert_Element <ValueType elem_type, ValueType vec_type,
(INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
>;
+// Vector Build pattern
+class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat <
+ (IL_vbuild elemClass:$src),
+ (INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x)
+>;
+
// bitconvert pattern
class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
(dt (bitconvert (st rc:$src0))),
diff --git a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
deleted file mode 100644
index d129a3b..0000000
--- a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
+++ /dev/null
@@ -1,88 +0,0 @@
-//===-- AMDGPULowerInstructions.cpp - AMDGPU lowering pass ----------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass lowers unsupported AMDIL MachineInstrs to LLVM pseudo
-// MachineInstrs for hw codegen targets.
-//
-//===----------------------------------------------------------------------===//
-
-
-#include "AMDGPU.h"
-#include "AMDGPURegisterInfo.h"
-#include "AMDIL.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
-using namespace llvm;
-
-namespace {
-
-class AMDGPULowerInstructionsPass : public MachineFunctionPass {
-
-private:
- static char ID;
- TargetMachine &TM;
- void lowerVCREATE_v4(MachineInstr &MI, MachineBasicBlock::iterator I,
- MachineBasicBlock &MBB, MachineFunction &MF);
-
-public:
- AMDGPULowerInstructionsPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm) { }
-
- virtual bool runOnMachineFunction(MachineFunction &MF);
-
- virtual const char *getPassName() const {return "AMDGPU Lower Instructions";}
-
-};
-
-} // End anonymous namespace
-
-char AMDGPULowerInstructionsPass::ID = 0;
-
-FunctionPass *llvm::createAMDGPULowerInstructionsPass(TargetMachine &tm) {
- return new AMDGPULowerInstructionsPass(tm);
-}
-
-bool AMDGPULowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
-{
- for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
- BB != BB_E; ++BB) {
- MachineBasicBlock &MBB = *BB;
- for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
- I != MBB.end(); I = Next, Next = llvm::next(I) ) {
- MachineInstr &MI = *I;
-
- switch (MI.getOpcode()) {
- default: continue;
- case AMDIL::VCREATE_v4f32:
- case AMDIL::VCREATE_v4i32:
- lowerVCREATE_v4(MI, I, MBB, MF); break;
- }
- MI.eraseFromParent();
- }
- }
- return false;
-}
-
-void AMDGPULowerInstructionsPass::lowerVCREATE_v4(MachineInstr &MI,
- MachineBasicBlock::iterator I, MachineBasicBlock &MBB, MachineFunction &MF)
-{
- MachineRegisterInfo & MRI = MF.getRegInfo();
- unsigned tmp = MRI.createVirtualRegister(
- MRI.getRegClass(MI.getOperand(0).getReg()));
-
- BuildMI(MBB, I, DebugLoc(), TM.getInstrInfo()->get(AMDIL::IMPLICIT_DEF), tmp);
-
- BuildMI(MBB, I, DebugLoc(), TM.getInstrInfo()->get(AMDIL::INSERT_SUBREG))
- .addOperand(MI.getOperand(0))
- .addReg(tmp)
- .addOperand(MI.getOperand(1))
- .addImm(AMDIL::sel_x);
-}
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index b4d2a2f..c6a2412 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -138,7 +138,6 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
if (ST.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
PM->add(createSIAssignInterpRegsPass(*TM));
}
- PM->add(createAMDGPULowerInstructionsPass(*TM));
PM->add(createAMDGPUConvertToISAPass(*TM));
return false;
}
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 586d18d..afddefe 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -732,12 +732,6 @@ def LCREATE_v2i64 : TwoInOneOut<IL_OP_I_ADD, (outs GPRV2I64:$dst),
[(set GPRV2I64:$dst,
(IL_lcreate2 GPRV2I32:$src0, GPRV2I32:$src1))]>;
//===---------------------------------------------------------------------===//
-// Scalar ==> Vector conversion functions
-//===---------------------------------------------------------------------===//
-// This opcode has custom swizzle pattern encoded in Swizzle Encoder
-defm VCREATE : UnaryOpMCVec<IL_OP_MOV, IL_vbuild>;
-
-//===---------------------------------------------------------------------===//
// Vector ==> Scalar conversion functions
//===---------------------------------------------------------------------===//
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 9742e6b..b5665ce 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -33,7 +33,6 @@ CPP_SOURCES := \
AMDGPUTargetMachine.cpp \
AMDGPUISelLowering.cpp \
AMDGPUConvertToISA.cpp \
- AMDGPULowerInstructions.cpp \
AMDGPUInstrInfo.cpp \
AMDGPURegisterInfo.cpp \
AMDGPUUtil.cpp \
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 27744d1..9caaf1c 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -1122,6 +1122,9 @@ def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
+def : Vector_Build <v4f32, R600_Reg32>;
+def : Vector_Build <v4i32, R600_Reg32>;
+
// bitconvert patterns
def : BitConvert <i32, f32, R600_Reg32>;
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 4408777..8fd0c49 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -905,6 +905,9 @@ def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 5, sel_y>;
def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 6, sel_z>;
def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 7, sel_w>;
+def : Vector_Build <v4f32, VReg_32>;
+def : Vector_Build <v4i32, SReg_32>;
+
/*
def : Pat<
(int_SI_vs_load_buffer_index),
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