Mesa (master): radeon/llvm: Remove deadcode from the AMDILISelLowering class
Tom Stellard
tstellar at kemper.freedesktop.org
Wed Jun 6 13:50:20 UTC 2012
Module: Mesa
Branch: master
Commit: 1777c99bff40f160b09dd3c9708b0963c772610a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1777c99bff40f160b09dd3c9708b0963c772610a
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Sat Jun 2 09:51:04 2012 -0400
radeon/llvm: Remove deadcode from the AMDILISelLowering class
---
src/gallium/drivers/radeon/AMDILISelLowering.cpp | 119 ----------------------
src/gallium/drivers/radeon/AMDILISelLowering.h | 84 ---------------
2 files changed, 0 insertions(+), 203 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
index 018f97e..1c5c9ba 100644
--- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
@@ -1482,11 +1482,6 @@ AMDILTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
return Op;
}
-int
-AMDILTargetLowering::getVarArgsFrameOffset() const
-{
- return VarArgsFrameOffset;
-}
#undef LOWER
SDValue
@@ -3323,51 +3318,6 @@ AMDILTargetLowering::getFunctionAlignment(const Function *) const
return 0;
}
-void
-AMDILTargetLowering::setPrivateData(MachineBasicBlock *BB,
- MachineBasicBlock::iterator &BBI,
- DebugLoc *DL, const TargetInstrInfo *TII) const
-{
- mBB = BB;
- mBBI = BBI;
- mDL = DL;
- mTII = TII;
-}
-uint32_t
-AMDILTargetLowering::genVReg(uint32_t regType) const
-{
- return mBB->getParent()->getRegInfo().createVirtualRegister(
- getTargetMachine().getRegisterInfo()->getRegClass(regType));
-}
-
-MachineInstrBuilder
-AMDILTargetLowering::generateMachineInst(uint32_t opcode, uint32_t dst) const
-{
- return BuildMI(*mBB, mBBI, *mDL, mTII->get(opcode), dst);
-}
-
-MachineInstrBuilder
-AMDILTargetLowering::generateMachineInst(uint32_t opcode, uint32_t dst,
- uint32_t src1) const
-{
- return generateMachineInst(opcode, dst).addReg(src1);
-}
-
-MachineInstrBuilder
-AMDILTargetLowering::generateMachineInst(uint32_t opcode, uint32_t dst,
- uint32_t src1, uint32_t src2) const
-{
- return generateMachineInst(opcode, dst, src1).addReg(src2);
-}
-
-MachineInstrBuilder
-AMDILTargetLowering::generateMachineInst(uint32_t opcode, uint32_t dst,
- uint32_t src1, uint32_t src2, uint32_t src3) const
-{
- return generateMachineInst(opcode, dst, src1, src2).addReg(src3);
-}
-
-
SDValue
AMDILTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const
{
@@ -3523,75 +3473,6 @@ AMDILTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const
}
SDValue
-AMDILTargetLowering::LowerUDIV24(SDValue Op, SelectionDAG &DAG) const
-{
- DebugLoc DL = Op.getDebugLoc();
- EVT OVT = Op.getValueType();
- SDValue LHS = Op.getOperand(0);
- SDValue RHS = Op.getOperand(1);
- MVT INTTY;
- MVT FLTTY;
- if (!OVT.isVector()) {
- INTTY = MVT::i32;
- FLTTY = MVT::f32;
- } else if (OVT.getVectorNumElements() == 2) {
- INTTY = MVT::v2i32;
- FLTTY = MVT::v2f32;
- } else if (OVT.getVectorNumElements() == 4) {
- INTTY = MVT::v4i32;
- FLTTY = MVT::v4f32;
- }
-
- // The LowerUDIV24 function implements the following CL.
- // int ia = (int)LHS
- // float fa = (float)ia
- // int ib = (int)RHS
- // float fb = (float)ib
- // float fq = native_divide(fa, fb)
- // fq = trunc(fq)
- // float t = mad(fq, fb, fb)
- // int iq = (int)fq - (t <= fa)
- // return (type)iq
-
- // int ia = (int)LHS
- SDValue ia = DAG.getZExtOrTrunc(LHS, DL, INTTY);
-
- // float fa = (float)ia
- SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
-
- // int ib = (int)RHS
- SDValue ib = DAG.getZExtOrTrunc(RHS, DL, INTTY);
-
- // float fb = (float)ib
- SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
-
- // float fq = native_divide(fa, fb)
- SDValue fq = DAG.getNode(AMDILISD::DIV_INF, DL, FLTTY, fa, fb);
-
- // fq = trunc(fq)
- fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
-
- // float t = mad(fq, fb, fb)
- SDValue t = DAG.getNode(AMDILISD::MAD, DL, FLTTY, fq, fb, fb);
-
- // int iq = (int)fq - (t <= fa) // This is sub and not add because GPU returns 0, -1
- SDValue iq;
- fq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
- if (INTTY == MVT::i32) {
- iq = DAG.getSetCC(DL, INTTY, t, fa, ISD::SETOLE);
- } else {
- iq = DAG.getSetCC(DL, INTTY, t, fa, ISD::SETOLE);
- }
- iq = DAG.getNode(ISD::ADD, DL, INTTY, fq, iq);
-
-
- // return (type)iq
- iq = DAG.getZExtOrTrunc(iq, DL, OVT);
- return iq;
-
-}
-
-SDValue
AMDILTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const
{
DebugLoc DL = Op.getDebugLoc();
diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.h b/src/gallium/drivers/radeon/AMDILISelLowering.h
index 5743987..f2b68d1 100644
--- a/src/gallium/drivers/radeon/AMDILISelLowering.h
+++ b/src/gallium/drivers/radeon/AMDILISelLowering.h
@@ -214,8 +214,6 @@ namespace llvm
class AMDILTargetLowering : public TargetLowering
{
- private:
- int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
AMDILTargetLowering(TargetMachine &TM);
@@ -333,30 +331,15 @@ namespace llvm
genu64tof64(SDValue Op, EVT dblvt, SelectionDAG &DAG) const;
SDValue
- LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
SDValue
- LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue
- LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG& DAG) const;
-
- SDValue
- LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG& DAG) const;
-
- SDValue
- LowerINTRINSIC_VOID(SDValue Op, SelectionDAG& DAG) const;
-
- SDValue
LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue
@@ -366,9 +349,6 @@ namespace llvm
LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
SDValue
- LowerADD(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
LowerSUB(SDValue Op, SelectionDAG &DAG) const;
SDValue
@@ -403,15 +383,6 @@ namespace llvm
LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
SDValue
- LowerUDIV(SDValue Op, SelectionDAG &DAG) const;
- SDValue
- LowerUDIV24(SDValue Op, SelectionDAG &DAG) const;
- SDValue
- LowerUDIV32(SDValue Op, SelectionDAG &DAG) const;
- SDValue
- LowerUDIV64(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
SDValue
LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
@@ -440,18 +411,9 @@ namespace llvm
LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
SDValue
- LowerAND(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
- LowerOR(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue
- LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue
@@ -461,9 +423,6 @@ namespace llvm
genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
SDValue
- LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
-
- SDValue
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue
@@ -473,49 +432,6 @@ namespace llvm
LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue
LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
- void
- generateCMPInstr(MachineInstr*, MachineBasicBlock*,
- const TargetInstrInfo&) const;
- MachineOperand
- convertToReg(MachineOperand) const;
-
- // private members used by the set of instruction generation
- // functions, these are marked mutable as they are cached so
- // that they don't have to constantly be looked up when using the
- // generateMachineInst/genVReg instructions. This is to simplify
- // the code
- // and to make it cleaner. The object itself doesn't change as
- // only these functions use these three data types.
- mutable MachineBasicBlock *mBB;
- mutable DebugLoc *mDL;
- mutable const TargetInstrInfo *mTII;
- mutable MachineBasicBlock::iterator mBBI;
- void
- setPrivateData(MachineBasicBlock *BB,
- MachineBasicBlock::iterator &BBI,
- DebugLoc *DL,
- const TargetInstrInfo *TII) const;
- uint32_t genVReg(uint32_t regType) const;
- MachineInstrBuilder
- generateMachineInst(uint32_t opcode,
- uint32_t dst) const;
- MachineInstrBuilder
- generateMachineInst(uint32_t opcode,
- uint32_t dst, uint32_t src1) const;
- MachineInstrBuilder
- generateMachineInst(uint32_t opcode,
- uint32_t dst, uint32_t src1, uint32_t src2) const;
- MachineInstrBuilder
- generateMachineInst(uint32_t opcode,
- uint32_t dst, uint32_t src1, uint32_t src2,
- uint32_t src3) const;
- uint32_t
- addExtensionInstructions(
- uint32_t reg, bool signedShift,
- unsigned int simpleVT) const;
- void
- generateLongRelational(MachineInstr *MI,
- unsigned int opCode) const;
}; // AMDILTargetLowering
} // end namespace llvm
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