Mesa (master): radeon/llvm: Use a custom inserter to lower LOAD_INPUT

[Tom Stellard]

Module: Mesa
Branch: master
Commit: ad385c402e665b2aedc7b456575d19df32584e73
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad385c402e665b2aedc7b456575d19df32584e73

Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Tue May  8 10:01:58 2012 -0400

radeon/llvm: Use a custom inserter to lower LOAD_INPUT

---

 src/gallium/drivers/radeon/AMDGPUInstructions.td   |    6 -----
 src/gallium/drivers/radeon/R600ISelLowering.cpp    |    9 ++++++-
 src/gallium/drivers/radeon/R600Instructions.td     |   15 +++++------
 .../drivers/radeon/R600LowerShaderInstructions.cpp |   24 --------------------
 4 files changed, 15 insertions(+), 39 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index f5b87f3..d126c79 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -42,12 +42,6 @@ let isCodeGenOnly = 1 in {
     [(int_AMDGPU_export_reg GPRF32:$src)]
   >;
 
-  def LOAD_INPUT : AMDGPUShaderInst <
-    (outs GPRF32:$dst),
-    (ins i32imm:$src),
-    "LOAD_INPUT $dst, $src",
-    [] >;
-
   def MASK_WRITE : AMDGPUShaderInst <
     (outs),
     (ins GPRF32:$src),
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 9e3b6b5..d35669e 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -88,8 +88,15 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
   case AMDIL::LOCAL_SIZE_Z:
     lowerImplicitParameter(MI, *BB, MRI, 8);
     break;
+  case AMDIL::LOAD_INPUT:
+    {
+      int64_t RegIndex = MI->getOperand(1).getImm();
+      addLiveIn(MI, MF, MRI, TII,
+                AMDIL::R600_TReg32RegClass.getRegister(RegIndex));
+      MI->eraseFromParent();
+      break;
+    }
   }
-  MI->eraseFromParent();
   return BB;
 }
 
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 381ad71..b462a05 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -991,6 +991,13 @@ def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
                                     int_r600_read_local_size_z>;
 
+def LOAD_INPUT : AMDGPUShaderInst <
+  (outs R600_Reg32:$dst),
+  (ins i32imm:$src),
+  "LOAD_INPUT $dst, $src",
+  [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
+>;
+
 } // End usesCustomInserter = 1, isPseudo = 1
 
 } // End isCodeGenOnly = 1
@@ -1032,12 +1039,4 @@ def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
 
 include "R600ShaderPatterns.td"
 
-// We need this pattern to avoid having real registers in PHI nodes.
-// For some reason this pattern only works when it comes after the other
-// instruction defs.
-def : Pat <
-  (int_R600_load_input imm:$src),
-  (LOAD_INPUT imm:$src)
->;
-
 } // End isR600toCayman Predicate
diff --git a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
index 742b50f..808f08c 100644
--- a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
@@ -32,7 +32,6 @@ namespace {
 
     void lowerEXPORT_REG_FAKE(MachineInstr &MI, MachineBasicBlock &MBB,
         MachineBasicBlock::iterator I);
-    void lowerLOAD_INPUT(MachineInstr & MI);
     bool lowerSTORE_OUTPUT(MachineInstr & MI, MachineBasicBlock &MBB,
         MachineBasicBlock::iterator I);
 
@@ -81,11 +80,6 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
         deleteInstr = true;
         break;
 
-      case AMDIL::LOAD_INPUT:
-        lowerLOAD_INPUT(MI);
-        deleteInstr = true;
-        break;
-
       case AMDIL::STORE_OUTPUT:
         deleteInstr = lowerSTORE_OUTPUT(MI, MBB, I);
         break;
@@ -103,24 +97,6 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
   return false;
 }
 
-/* The goal of this function is to replace the virutal destination register of
- * a LOAD_INPUT instruction with the correct physical register that will.
- *
- * XXX: I don't think this is the right way things assign physical registers,
- * but I'm not sure of another way to do this.
- */
-void R600LowerShaderInstructionsPass::lowerLOAD_INPUT(MachineInstr &MI)
-{
-  MachineOperand &dst = MI.getOperand(0);
-  MachineOperand &arg = MI.getOperand(1);
-  int64_t inputIndex = arg.getImm();
-  const TargetRegisterClass * inputClass = TM.getRegisterInfo()->getRegClass(AMDIL::R600_TReg32RegClassID);
-  unsigned newRegister = inputClass->getRegister(inputIndex);
-  unsigned dstReg = dst.getReg();
-
-  AMDGPU::utilAddLiveIn(MI.getParent()->getParent(), *MRI, TM.getInstrInfo(), newRegister, dstReg);
-}
-
 bool R600LowerShaderInstructionsPass::lowerSTORE_OUTPUT(MachineInstr &MI,
     MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
 {