Mesa (master): radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg
Tom Stellard
tstellar at kemper.freedesktop.org
Thu May 10 16:51:30 UTC 2012
Module: Mesa
Branch: master
Commit: b0bb125736fd29dbad6cfa8d4de0c44eaf5e28ad
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0bb125736fd29dbad6cfa8d4de0c44eaf5e28ad
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu May 10 11:52:00 2012 -0400
radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg
---
src/gallium/drivers/radeon/R600CodeEmitter.cpp | 5 -----
src/gallium/drivers/radeon/R600Instructions.td | 12 ------------
2 files changed, 0 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
index eff18e2..df1dab5 100644
--- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
@@ -198,12 +198,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
switch(MI.getOpcode()) {
case AMDIL::RAT_WRITE_CACHELESS_eg:
{
- /* XXX: Support for autoencoding 64-bit instructions was added
- * in LLVM 3.1. Until we drop support for 3.0, we will use Magic
- * numbers for the high bits. */
- uint64_t high = 0x95c0100000000000;
uint64_t inst = getBinaryCodeForInstr(MI);
- inst |= high;
/* Set End Of Program bit */
/* XXX: Need better check of end of program. EOP should be
* encoded in one of the operands of the MI, and it should be
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index e3ed7c2..aa67c6d 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -152,8 +152,6 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
let Inst{31-30} = ELEM_SIZE;
/* CF_ALLOC_EXPORT_WORD1_BUF */
-/* XXX: We can't have auto encoding of 64-bit instructions until LLVM 3.1 :( */
-/*
let Inst{43-32} = ARRAY_SIZE;
let Inst{47-44} = COMP_MASK;
let Inst{51-48} = BURST_COUNT;
@@ -162,7 +160,6 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
let Inst{61-54} = cf_inst;
let Inst{62} = MARK;
let Inst{63} = BARRIER;
-*/
}
/*
@@ -745,20 +742,12 @@ def RAT_WRITE_CACHELESS_eg :
EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
{
-/*
- let Inst{3-0} = RAT_ID;
- let Inst{21-15} = RW_GPR;
- let Inst{29-23} = INDEX_GPR;
- /* Propery of the UAV */
- let Inst{31-30} = ELEM_SIZE;
-*/
let RIM = 0;
/* XXX: Have a separate instruction for non-indexed writes. */
let TYPE = 1;
let RW_REL = 0;
let ELEM_SIZE = 0;
-/*
let ARRAY_SIZE = 0;
let COMP_MASK = 1;
let BURST_COUNT = 0;
@@ -766,7 +755,6 @@ def RAT_WRITE_CACHELESS_eg :
let EOP = 0;
let MARK = 0;
let BARRIER = 1;
-*/
}
def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
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