Mesa (master): radeon/llvm: Remove AMDIL MAD instruction defs
Tom Stellard
tstellar at kemper.freedesktop.org
Thu May 17 20:21:30 UTC 2012
Module: Mesa
Branch: master
Commit: ef8e66bc165ea2ef9987ab6406268ce195f74eb0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef8e66bc165ea2ef9987ab6406268ce195f74eb0
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu May 17 14:34:40 2012 -0400
radeon/llvm: Remove AMDIL MAD instruction defs
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl | 1 -
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 3 +++
src/gallium/drivers/radeon/AMDILInstructions.td | 2 --
src/gallium/drivers/radeon/R600Instructions.td | 6 +++---
src/gallium/drivers/radeon/SIInstrInfo.cpp | 1 -
src/gallium/drivers/radeon/SIInstructions.td | 8 ++++++++
6 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index df532eb..52b79bd 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -34,7 +34,6 @@ use strict;
my @F32_MULTICLASSES = qw {
UnaryIntrinsicFloat
UnaryIntrinsicFloatScalar
- TernaryIntrinsicFloat
};
my @I32_MULTICLASSES = qw {
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 921daa6..53f04c5 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -45,6 +45,9 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
default: return Op;
case AMDGPUIntrinsic::AMDIL_abs:
return LowerIntrinsicIABS(Op, DAG);
+ case AMDGPUIntrinsic::AMDIL_mad:
+ return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
+ Op.getOperand(2), Op.getOperand(3));
case AMDGPUIntrinsic::AMDIL_max:
return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
Op.getOperand(2));
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 725ac29..629a2c0 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -251,7 +251,6 @@ defm POW : BinaryIntrinsicFloat<IL_OP_POW, int_AMDIL_pow>;
let hasIEEEFlag = 1 in {
let mayLoad = 0, mayStore=0 in {
defm MIN : BinaryIntrinsicFloat<IL_OP_MIN, int_AMDIL_min>;
-defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
}
defm MOD : BinaryOpMCf32<IL_OP_MOD, frem>;
}
@@ -270,7 +269,6 @@ defm LERP : TernaryIntrinsicFloat<IL_OP_LERP, int_AMDIL_lerp>;
}
defm SUB : BinaryOpMCf32<IL_OP_SUB, fsub>;
defm FABS : UnaryOpMCf32<IL_OP_ABS, fabs>;
-defm FMAD : TernaryOpMCf32<IL_OP_MAD, IL_mad>;
defm NEAR : UnaryOpMCf32<IL_OP_ROUND_NEAR, fnearbyint>;
defm RND_Z : UnaryOpMCf32<IL_OP_ROUND_ZERO, ftrunc>;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 75ccca2..df2d56b 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -521,9 +521,9 @@ class MUL_LIT_Common <bits<32> inst> : R600_3OP <
class MULADD_Common <bits<32> inst> : R600_3OP <
inst, "MULADD",
- []> {
- let AMDILOp = AMDILInst.MAD_f32;
-}
+ [(set (f32 R600_Reg32:$dst),
+ (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
+>;
class CNDE_Common <bits<32> inst> : R600_3OP <
inst, "CNDE",
diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp
index 0cb9764..553ac36 100644
--- a/src/gallium/drivers/radeon/SIInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp
@@ -106,7 +106,6 @@ MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
{
switch (AMDILopcode) {
- case AMDIL::MAD_f32: return AMDIL::V_MAD_LEGACY_F32;
//XXX We need a better way of detecting end of program
case AMDIL::RETURN: return AMDIL::S_ENDPGM;
default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index c1c9699..1818e47 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -964,4 +964,12 @@ def : Pat <
/* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
+/********** ================== **********/
+/********** VOP3 Patterns **********/
+/********** ================== **********/
+
+def : Pat <(f32 (IL_mad AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2)),
+ (V_MAD_LEGACY_F32 AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2,
+ 0, 0, 0, 0)>;
+
} // End isSI predicate
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