Mesa (master): i915: Drop gen4+ code from the forked clear code.
Eric Anholt
anholt at kemper.freedesktop.org
Wed May 23 17:44:43 UTC 2012
Module: Mesa
Branch: master
Commit: 03c9044c2edf8301779fe5d0173d7e6d1e7ee1c2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03c9044c2edf8301779fe5d0173d7e6d1e7ee1c2
Author: Eric Anholt <eric at anholt.net>
Date: Mon May 21 09:13:33 2012 -0700
i915: Drop gen4+ code from the forked clear code.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
---
src/mesa/drivers/dri/i915/intel_clear.c | 11 +----------
1 files changed, 1 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_clear.c b/src/mesa/drivers/dri/i915/intel_clear.c
index 3316351..96d9c8f 100644
--- a/src/mesa/drivers/dri/i915/intel_clear.c
+++ b/src/mesa/drivers/dri/i915/intel_clear.c
@@ -89,9 +89,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
struct intel_renderbuffer *irb;
int i;
- if (!_mesa_check_conditional_render(ctx))
- return;
-
if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
intel->front_buffer_dirty = true;
}
@@ -116,7 +113,7 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
}
/* HW color buffers (front, back, aux, generic FBO, etc) */
- if (intel->gen < 6 && colorMask == ~0) {
+ if (colorMask == ~0) {
/* clear all R,G,B,A */
blit_mask |= (mask & BUFFER_BITS_COLOR);
}
@@ -143,12 +140,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
*/
tri_mask |= BUFFER_BIT_STENCIL;
}
- else if (intel->has_separate_stencil &&
- stencilRegion->tiling == I915_TILING_NONE) {
- /* The stencil buffer is actually W tiled, which the hardware
- * cannot blit to. */
- tri_mask |= BUFFER_BIT_STENCIL;
- }
else {
/* clearing all stencil bits, use blitting */
blit_mask |= BUFFER_BIT_STENCIL;
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