Mesa (master): radeon/llvm: Fix instruction encoding for r600 family GPUs
Tom Stellard
tstellar at kemper.freedesktop.org
Mon Sep 24 21:09:06 UTC 2012
Module: Mesa
Branch: master
Commit: 92b033a89ebd46d640ecb2592159087a87e5516e
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=92b033a89ebd46d640ecb2592159087a87e5516e
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Sep 24 16:49:43 2012 -0400
radeon/llvm: Fix instruction encoding for r600 family GPUs
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
https://bugs.freedesktop.org/show_bug.cgi?id=55217
---
.../radeon/MCTargetDesc/R600MCCodeEmitter.cpp | 4 ++--
src/gallium/drivers/radeon/R600Defines.h | 12 ++++++++++++
src/gallium/drivers/radeon/R600InstrInfo.h | 13 -------------
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
index 847fcb6..a11f482 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -218,8 +218,8 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
//older alu have different encoding for instructions with one or two src
//parameters.
- if (STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst &&
- MI.getNumOperands() < 4) {
+ if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
+ !(MCDesc.TSFlags & R600_InstFlag::OP3)) {
uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
InstWord01 &= ~(0x3FFULL << 39);
InstWord01 |= ISAOpCode << 1;
diff --git a/src/gallium/drivers/radeon/R600Defines.h b/src/gallium/drivers/radeon/R600Defines.h
index 655b984..20c357c 100644
--- a/src/gallium/drivers/radeon/R600Defines.h
+++ b/src/gallium/drivers/radeon/R600Defines.h
@@ -21,3 +21,15 @@
// operand.
#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
+namespace R600_InstFlag {
+ enum TIF {
+ TRANS_ONLY = (1 << 0),
+ TEX = (1 << 1),
+ REDUCTION = (1 << 2),
+ FC = (1 << 3),
+ TRIG = (1 << 4),
+ OP3 = (1 << 5),
+ VECTOR = (1 << 6)
+ //FlagOperand bits 7, 8
+ };
+}
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h
index bfe8d03..de82542 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.h
+++ b/src/gallium/drivers/radeon/R600InstrInfo.h
@@ -129,17 +129,4 @@ namespace llvm {
} // End llvm namespace
-namespace R600_InstFlag {
- enum TIF {
- TRANS_ONLY = (1 << 0),
- TEX = (1 << 1),
- REDUCTION = (1 << 2),
- FC = (1 << 3),
- TRIG = (1 << 4),
- OP3 = (1 << 5),
- VECTOR = (1 << 6)
- //FlagOperand bits 7, 8
- };
-}
-
#endif // R600INSTRINFO_H_
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