Mesa (master): i965: Don't spill "smeared" registers.
Kenneth Graunke
kwg at kemper.freedesktop.org
Tue Sep 25 14:15:33 UTC 2012
Module: Mesa
Branch: master
Commit: ab5ce2789fe9e5f2789ee22fdb02bcfed42a7125
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab5ce2789fe9e5f2789ee22fdb02bcfed42a7125
Author: Paul Berry <stereotype441 at gmail.com>
Date: Wed Sep 19 13:28:00 2012 -0700
i965: Don't spill "smeared" registers.
Fixes an assertion failure when compiling certain shaders that need both
pull constants and register spilling:
brw_eu_emit.c:204: validate_reg: Assertion `execsize >= width' failed.
NOTE: This is a candidate for release branches.
Signed-off-by: Paul Berry <stereotype441 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index b0d4124..37c8917 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -317,11 +317,26 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF) {
spill_costs[inst->src[i].reg] += loop_scale;
+
+ /* Register spilling logic assumes full-width registers; smeared
+ * registers have a width of 1 so if we try to spill them we'll
+ * generate invalid assembly. This shouldn't be a problem because
+ * smeared registers are only used as short-term temporaries when
+ * loading pull constants, so spilling them is unlikely to reduce
+ * register pressure anyhow.
+ */
+ if (inst->src[i].smear >= 0) {
+ no_spill[inst->src[i].reg] = true;
+ }
}
}
if (inst->dst.file == GRF) {
spill_costs[inst->dst.reg] += inst->regs_written() * loop_scale;
+
+ if (inst->dst.smear >= 0) {
+ no_spill[inst->dst.reg] = true;
+ }
}
switch (inst->opcode) {
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