Mesa (9.0): i965/blorp: don' t reduce stencil alignment restrictions when multisampling.

[Paul Berry]

Module: Mesa
Branch: 9.0
Commit: 62bc4af0e18f76dd30a4d5ae6d45a365a1fa226f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=62bc4af0e18f76dd30a4d5ae6d45a365a1fa226f

Author: Paul Berry <stereotype441 at gmail.com>
Date:   Wed Aug 29 15:11:49 2012 -0700

i965/blorp: don't reduce stencil alignment restrictions when multisampling.

When blitting to a stencil buffer, we need to align the rectangle we
send down the rendering pipeline, to account for the fact that the
stencil buffer uses a W-tiled layout, but we are configuring its
surface state as Y-tiled.

Previously, when the stencil buffer was multisampled, we assumed that
we could reduce the amount of alignment that was necessary, since each
pixel occupies a block of 2x2 or 4x2 samples in the stencil buffer.
That would have been correct if the coordinates we were adjusting were
measured in pixels.  However, the conversion from pixel coordinates to
coordinates within the interleaved buffer has already been done;
therefore the full alignment restriction applies.

Note: the reason this mistake wasn't previously uncovered by piglit
tests is because it is being masked by another mistake: the blorp
engine is using overly conservative alignment restrictions when doing
stencil blits.  The overly conservative alignment restrictions will be
removed in the patch that follows.  Doing this fix now will prevent
the subsequent patch from introducing regressions.

Acked-by: Eric Anholt <eric at anholt.net>
(cherry picked from commit 1a75063d5f829547b75b60ae64bddf3905b4cb8f)

---

 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |   10 +---------
 1 files changed, 1 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index ede78cc..67274dc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1785,18 +1785,10 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
        * differences between W and Y tiling formats will mean that pixels are
        * scrambled within the tile.
        *
-       * Note: if the destination surface configured to use IMS layout, then
-       * the effective tile size we need to align it to is smaller, because
-       * each pixel covers a 2x2 or a 4x2 block of samples.
-       *
        * TODO: what if this makes the coordinates (or the texture size) too
        * large?
        */
-      unsigned x_align = 64, y_align = 64;
-      if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
-         x_align /= (dst_mt->num_samples == 4 ? 2 : 4);
-         y_align /= 2;
-      }
+      const unsigned x_align = 64, y_align = 64;
       x0 = ROUND_DOWN_TO(x0, x_align) * 2;
       y0 = ROUND_DOWN_TO(y0, y_align) / 2;
       x1 = ALIGN(x1, x_align) * 2;