Mesa (master): r600g: force full cache for hyperz

[Jerome Glisse]

Module: Mesa
Branch: master
Commit: c7a13dc5f530783e2ec22af2e1d7206b4754da48
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7a13dc5f530783e2ec22af2e1d7206b4754da48

Author: Jerome Glisse <jglisse at redhat.com>
Date:   Wed Apr 24 19:15:52 2013 -0400

r600g: force full cache for hyperz

Seems that in some case allowing half cache usage confuse the gpu
and trigger lockup. Force full cache use.

Should fix :
https://bugs.freedesktop.org/show_bug.cgi?id=59592
https://bugs.freedesktop.org/show_bug.cgi?id=60848
https://bugs.freedesktop.org/show_bug.cgi?id=60969
https://bugs.freedesktop.org/show_bug.cgi?id=61747
https://bugs.freedesktop.org/show_bug.cgi?id=62466
https://bugs.freedesktop.org/show_bug.cgi?id=62669
https://bugs.freedesktop.org/show_bug.cgi?id=62721
https://bugs.freedesktop.org/show_bug.cgi?id=63124

Signed-off-by: Jerome Glisse <jglisse at redhat.com>

---

 src/gallium/drivers/r600/evergreen_state.c |    1 +
 src/gallium/drivers/r600/r600_state.c      |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 13f0678..6797b22 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1691,6 +1691,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
 		surf->db_htile_data_base = va >> 8;
 		surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
 					S_028ABC_HTILE_HEIGHT(1) |
+					S_028ABC_FULL_CACHE(1) |
 					S_028ABC_LINEAR(1);
 		surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
 		surf->db_preload_control = 0;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b054fef..4e0e4a6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1532,6 +1532,7 @@ static void r600_init_depth_surface(struct r600_context *rctx,
 		surf->db_htile_data_base = va >> 8;
 		surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
 					S_028D24_HTILE_HEIGHT(1) |
+					S_028D24_FULL_CACHE(1) |
 					S_028D24_LINEAR(1);
 		/* preload is not working properly on r6xx/r7xx */
 		surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);