Mesa (broadwell): 112 new commits
Kenneth Graunke
kwg at kemper.freedesktop.org
Wed Nov 6 09:29:00 UTC 2013
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc49365466f6128bb9ef6803a3fcd432dcfce0ad
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:41:34 2013 -0700
i965: Add Broadwell PCI IDs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4b7a9d58292dcba307bd9b7003b21446bd6db13
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 23:19:55 2013 -0800
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes:
- 48-bit relocations
- Thread count is specified as U/2-1 instead of U-1.
- An extra DWord (DW9) with clip planes, URB entry output length/offsets
- We need to program the "Expected Vertex Count" (VerticesIn)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea9a6d9ace6a364ada1840592782849607f19811
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 16:12:50 2013 -0800
more SOL updates...for XFB2/3/instanced
XXX: Need to store {0, 0, 0, 0} in offset_bo at beginXFB time.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61e65ff13cc542e7a74df01fca6e632f9475c99a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 14:09:07 2013 -0800
i965: Skip the register write check on Broadwell.
MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code
doesn't work. But supposedly Broadwell has a register whitelist and
just works out of the box anyway, so there's no need to check.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18687b755192e5e09c57b5f46c8b7b3df7febaef
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:20:37 2012 -0800
i965: Update multisampling state for Broadwell.
On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x). It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.
Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN. With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.
Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7. This patch, however, does not implement 2x
and 16x.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a28ddcc89989e8334e293611aab19067ad3263c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 22 12:20:31 2013 -0800
i965: Fix texture border color on Broadwell.
The Gen7 sampler state code still works. Increasing the alignment to
64 bytes makes bit 5 zero, which is good because it's now reserved.
Since we don't use the new filter bits, we can leave those as zero too,
which means we don't need to update the code to update the pointer.
(We probably should anyway, for clarity, but alas, another day.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5e09990181a0f5ce627322501320c9153db35f7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jan 20 08:58:14 2013 -0800
i965: Don't use MACH for integer multiplies on Gen8+.
The documentation is really hard to follow, but apparently a 32-bit x
32-bit multiply just works without the MACH macro. The macro apparently
is only necessary to get the full 64-bit value.
Fixes Piglit tests [vf]s-op-mult-int-int.shader_test.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59ca485e6ccccfad60c664af626622e5f6e17801
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 14 21:43:28 2013 -0800
i965: Fix texture swizzling on Broadwell.
Like Haswell, we do this in SURFACE_STATE rather than shader
workarounds.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb61bcbbf0fa57b7e3e8df467059aa1f6ef3f0fe
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 12 16:12:38 2013 -0800
i965: Workaround 64-bit relocations in blitter code.
Emit zeros for the high 16 bits of each address. This is not what we
want long term, but gets things working for now.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=208623c115029e734ca9c52c4b2aac5562764395
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 03:58:30 2012 -0800
i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.
(This patch was written before Paul's refactor to reuse
brw_emit_depthbuffer and just implement a gen7_emit_depth_stencil_hiz
function. We should probably rearchitect it to fit that new model, as
it's much better. --Ken)
(The rest of this commit message was written by Chad.)
The depth buffer packet emitted by this patchis incomplete.
We must use the packet's level/layer fields to specify the miptree slice
into which to render. This patch emits 0 there, and hence all rendering
occurs to the miptree's base slice. (In gen5 through gen7, we used the
intra-tile x/y offsets to specify the miptree slice. But gen8 removed
those fields.)
However, the incomplete implementation does show some signs of life. It
fixes the page fault in piglit:fbo-depth. (The test's segfault was
likely due to the high 16 bits of the surface base address being
invalid).
v2: [chadv]
- Comment in patch that depth buffer packet needs level/layer
fields.
- Remove comments specific to gen7.
- Expand commit message.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69c06dc3c3776cccf614c0c14fc12cd4fdca95a3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 19:30:26 2012 -0800
i965: Update BLEND_STATE for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b9e882249a971a0a0fdeb7ca3221047859f9e1d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 15:34:34 2012 -0800
i965: Update SF_CLIP_VIEWPORT for Broadwell.
It has more fields now. Not sure if this is correct for render_to_fbo.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffcdf254884d75b3f7cb74b33f099ecb51d41219
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Dec 15 01:14:03 2012 -0800
i965: Set vertical alignment unit to 4 on Broadwell.
Broadwell doesn't support a surface vertical alignment of 2. It only
supports VALIGN_4, VALIGN_8, or VALIGN_16. I chose 4 since it's the
least wasteful.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8c7ff3e00f2fd20c9ecb63863db9520757922bc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 16:39:03 2012 -0800
i965: Rework SURFACE_STATE entries for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=09b76ed9b734268578f9adf3a21b49971abd962c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 14:45:19 2012 -0800
i965: Update SOL state for Broadwell.
Unlike on Gen7, we can directly set the offset via the state packet.
We also -have- to: the kernel SOL reset code won't work anymore.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ec5d06f740780f18d3ad815cda7eb3a5a4a73b6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:39:19 2012 -0800
i965: Update the code that disables unused shader stages for Broadwell.
This may or may not be necessary, but it shouldn't hurt.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bfb6c0870c748b21dede2cdcacc6e6cadbb6e86
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 11:39:14 2012 -0800
i965: Double the push constant space multipliers on Broadwell too.
Broadwell has 2Kb push constant size increments like Haswell GT3.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d7ac28297028dbd44be63213d98a2a3727b8820
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 16:29:33 2013 -0700
i965: Update 3DSTATE_CLIP for Broadwell.
Broadwell doesn't have GEN6_CLIP_Z_TEST, and doesn't make you specify
the polygon winding information (it pulls that information from other
packets).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e69d9e6eccbc0aea6c5ff4101ba08f92c7e31af
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 18:28:29 2012 -0800
i965: Rework vertex uploads for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a36b0b52765748d2f0b8172e2177f347299d4a5d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:28:39 2012 -0800
i965: Update invariant state for Broadwell.
The only difference is that STATE_SIP takes a 48-bit address, so we need
to output two zeroes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f62dfdcc4afef78aa089b948090f8c9aba35666
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 13:53:40 2012 -0800
i965: Update STATE_BASE_ADDRESS for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1cd409d461574362560d2b394210479f4c8b5d7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef5105b86b772d6747d0fc59d1107a412aa57ce3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:10:19 2012 -0800
i965: Rework 3DSTATE_VS for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01c7d1f9262e840bd72715e3604a2c0987c90e7e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 18:43:59 2012 -0800
i965: Add the new 3DSTATE_PS_BLEND state packet.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab3d99bf555ba1ae355eab6b226641aad2908c75
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 17:52:31 2012 -0800
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7ededff5d4741992152e82f1e1c1adb57178632
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 14:37:33 2013 -0700
i965: Update SF, SBE, and RASTER state for Broadwell.
The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f01098432a434cdbf74efd586f23aa2142750f5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 16:55:26 2013 -0800
i965: Introduce an OUT_RELOC64 macro.
Broadwell uses 48-bit addresses. The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.
Since individual buffers shouldn't be larger than 4GB in size, any
offsets into those buffers (buffer->offset + delta) should fit in the
low 32 bits. So I believe we can simply emit 0 for the high 16-bits,
and drm_intel_bo_emit_reloc() should patch it up.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c87516c537e141c7834e00d352d9b79038433d5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:50:22 2012 -0800
i965: Bump generation assertions on workaround flushes.
These workaround flushes may not be necessary on Gen8. Investigation is
needed. Tentatively, let's do them out of caution.
v2: [chadv]
- Comment that flush may not be needed.
- Make assertion conditions symmetrical.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b06fe707c6ad087d8088c243fff3eee87dc12df4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:30:01 2012 -0800
i965: Use the Sandybridge VUE format on Broadwell as well.
It hasn't changed.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=336ac27ce80b479db1f3b4bccd7d2716f0f9f276
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:16:18 2012 -0800
i965: Duplicate gen7_atoms to gen8_atoms.
It's going to diverge significantly. Starting out with a copy allows
future patches to change atoms one by one.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=197472e8d699e53968b52c0ae5a0d3c3a59167fe
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 16 00:40:30 2012 -0800
i965/vs: Don't copy propagate into SEND-from-GRF messages.
SEND can't deal with swizzles, source modifiers, and so on. This should
avoid problems with VS pull constant loads on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e409c0194c69fd5653b7e4150e538d71eb64c8b3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 16 00:02:43 2012 -0800
i965/vs: Always store pull constant offsets in GRFs on Gen8.
We need to SEND from a GRF, and we can only obtain those prior to
register allocation.
This allows us to do pull constant loads without the MRF hack.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8932568ddb6ea83ae608293297ab83bdbaa4da4f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:38:26 2012 -0800
i965: Create a new fragment shader backend for Broadwell.
This replaces the old fs_generator backend.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c54e6aca6a0036a09c41ff2abd4084019cf8403
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:37:34 2012 -0800
i965: Create a new vec4 backend for Broadwell.
This replaces the old vec4_generator backend.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53539da9e10151a3fdf625c00fbe97bd03a2b169
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:50 2012 -0800
i965: Add a new infrastructure for generating Broadwell shader assembly.
This replaces the brw_eu_emit.c layer for Broadwell. It will be
used by both the vector and scalar shader backends.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6340d33f64b72744cebac5cea528fad7cc361695
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 11 00:26:11 2012 -0800
i965: Implement a disassembler for Broadwell's new instruction encoding
Heavily based on Keith Packard's existing brw_disasm.c code. I've tried
to go through most of the pieces (like SFIDs) and update the lists to
include features added in recent generations.
I had to use C++ since my new instruction representation requires it.
Unfortunately, C++98 doesn't allow the use of C99 array initializers,
which makes the arrays mapping values to strings harder to read. I
tried to compensate for this failing by adding additional comments.
The disassembly can definitely be improved, but this should at least
get INTEL_DEBUG=vs/fs working.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db284fe33908f00f55591c8f4e7a79f3caf2d7ca
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:26 2012 -0800
i965: Add a new representation for Broadwell shader instructions.
Broadwell significantly changes the EU instruction encoding. Many of
the fields got moved to different bit positions; some even got split
in two.
With so many changes, it was infeasible to continue using struct
brw_instruction. We needed a new representation.
This new approach is a bit different: rather than a struct, I created a
class that has four DWords, and helper functions that read/write various
bits. This has several advantages:
1. We can create several different names for the same bits. For
example, conditional modifiers, SFID for SEND instructions, and the
MATH instruction's function opcode are all stored in bits 27:24.
In each situation, we can use the appropriate setter function:
set_sfid(), set_math_function(), or set_cond_modifier(). This
is much easier to follow.
2. Since the fields are expressed using the original 128-bit numbers,
the code to create the getter/setter functions follows the table in
the documentation very closely.
To aid in debugging, I've enabled -fkeep-inline-functions when building
gen8_instruction.cpp. Otherwise, these functions cannot be called by
gdb, making it insanely difficult to print out anything.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc36b0cc3b3aaed26253f8612c3005dfbf6a4af2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 5 16:55:06 2013 -0800
i965: Reserve space for "Vertex Count" in GS outputs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=48b8b7adc5b9142397d54d3a4d307366b413bbe5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 13:35:15 2012 -0800
i965: Disable BLORP on Broadwell for now.
BLORP is essential. However, porting it to Gen8 is a huge amount of
work. Disabling it for now allows us to proceed with basic hardware
enablement.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fc63d0037c8fa5a48e6f49152f342556e1e6f36
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 17:56:40 2012 -0800
i965: Disable HiZ on Broadwell for now.
HiZ is difficult to implement, and while it's essential for performance,
we don't need it right away for purposes of hardware enabling.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64cd26cda6b389dddadf98d462b002a46eee5ad6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:45:47 2013 -0700
i965: Claim OpenGL 3.3 support on Broadwell.
Bugs aside, basically everything ought to work.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=082f94e9cae2aad5f040bef36990907c9d69c13b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:44:09 2013 -0700
i965: Add device info structs for Broadwell.
As always, the chipset limits here are placeholders, rather than the
actual values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=05c94d71c4eab2838b925ea85778d44a21e18bdc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 14 21:26:28 2013 -0800
i965: Make swizzle_to_scs non-static.
We'll need this for Broadwell code as well.
Normally, when we make things public, we add the "brw" prefix. I'm not
crazy about that in this case, since it deals with prog_instruction.h's
SWIZZLE_XYZW values, rather than the BRW_SWIZZLE_XYZW enums. However,
I can't think of a better name, and at least the comments and code make
it clear.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ea645d747597daae1da4f66a48af441bc2967f7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 12:50:16 2013 -0700
i965: Move enum brw_urb_write_flags from brw_eu.h to brw_defines.h.
Broadwell code should not include brw_eu.h (since it is for Gen4-7
assembly encoding), but needs the URB write flags enum.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=22b8bb443e31b04de00e5e64043160bcaff4ea24
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 1 15:09:26 2013 -0800
i965/fs: Remove force_sechalf stack
Only Gen4 color write setup uses the force_sechalf flag, and it only
sets it on a single instruction. It also already has to get a pointer
to the instruction and manually set the saturate flag, so we may as well
just set force_sechalf the same way and avoid the complexity of a stack.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0155167b91ff67bdda430ba3a3ee8ffb9a8e2da
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 6 00:33:14 2013 -0800
i965: Use has_surface_tile_offset in depth/stencil alignment workaround.
Currently, has_surface_tile_offset is equivalent to gen == 4 && !is_g4x.
We already use it for related checks in brw_wm_surface_state.c, so it
makes sense to use it here too. It's simpler and more future-proof.
Broadwell also lacks surface tile offsets. With this patch, I won't
need to update any generation checking; I can simply not set the flag.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3785fe27158d1774a785b61c7cbbc90edbe0f9eb
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Wed Nov 6 19:35:41 2013 +1300
docs: Mark off ARB_sample_shading; minor tidyup.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7e15fcf56595aac99644292386a6e6d06dc6ec0
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Oct 27 12:32:03 2013 +1300
i965/fs: Gen4-5: Implement alpha test in shader for MRT
V2: Add comment explaining what emit_alpha_test() is for;
fix spurious temp and bogus whitespace.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca82ba90dd7ef78be2b95972dc19913c76d5e6a8
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Mon Oct 28 04:18:29 2013 +1300
i965/fs: Gen4-5: Setup discard masks for MRT alpha test
The same setup is required here as when the user-provided shader
explicitly uses KIL or discard.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1080fc610ef20e376c3a54b3cee2be911df9f012
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Oct 27 12:09:51 2013 +1300
i965: Gen4-5: Include alpha func/ref in program key
V2: Better explanation of the rationale for doing this.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbcd633040939565f91eedac6ea313503ac9f0a5
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Oct 27 12:09:51 2013 +1300
i965: Gen4-5: Don't enable hardware alpha test with MRT
We have to do this in the shader instead, since these gens lack an
independent RT0 alpha value in their render target write messages.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=39ebb72e52779b2975bfea3f08b91b7409f4a95c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 20:05:27 2013 -0700
i965: Combine {brw,gen7}_update_texture_buffer_surface() functions.
Now that brw_update_texture_buffer_surface() uses the virtual
emit_buffer_surface_state() function, it works for Gen7+ too.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a974a645e8b5c6a9aca3cc935a5a95cd9f33af8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 17:37:10 2013 -0700
i965: Unvirtualize brw_create_constant_surface; delete Gen7+ variant.
Now that brw_create_constant_surface uses a virtual function internally,
it doesn't need to be virtual itself. We can delete the Gen7+ variant
and simplify things.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee23dd139a7b76188c9245650e9f73d8b239e9c8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 17:33:42 2013 -0700
i965: Use the new emit_buffer_surface_state() vtable entry.
This will allow us to combine the Gen4-6 and Gen7 variants of these
functions.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba836e02a3f09cdc2188c45b6e409a936a840bea
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 25 11:37:06 2013 -0700
i965: Virtualize emit_buffer_surface_state().
This entails adding "mocs" and "rw" parameters to the Gen4-5 version.
I made it actually pay attention to the rw flag (even though it is
always false), but mocs is always ignored.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3854fe194021e61eff70c614550bbfc79d2b22e
Author: Courtney Goeltzenleuchter <courtney at lunarg.com>
Date: Wed Oct 30 15:58:30 2013 -0600
i965: Fix compiler warning.
fix: intel_screen.c:1320:4: warning: initialization from
incompatible pointer type [enabled by default]
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff337bc80069c74c6ad5d4ce84cd2029282d9e93
Author: Eric Anholt <eric at anholt.net>
Date: Fri Nov 1 17:43:43 2013 -0700
i965: Tell the unit states how many binding table entries we have.
Before the series with 3c9dc2d31b80fc73bffa1f40a91443a53229c8e2 to
dynamically assign our binding table indices, we didn't really track our
binding table count per shader, so we never filled in these fields.
Affects cairo-gl trace runtime by -2.47953% +/- 1.07281% (n=20)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f319eef76a31776085accb38c06851bc04f64b8
Author: Eric Anholt <eric at anholt.net>
Date: Mon Nov 4 15:49:52 2013 -0800
i965: Fix context initialization after 2f896627175384fd5
You can't return stack-initialized values and expect anything good to
happen.
Reviewed-by: Chad Versace <chad.versace at linux.intel.com
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ae31d7e1d3d51c7843571c63aa228f8ca9b879f
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Nov 5 19:21:25 2013 +0100
gallivm: optimize lp_build_minify for sse
SSE can't handle true vector shifts (with variable shift count),
so llvm is turning them into a mess of extracts, scalar shifts and inserts.
It is however possible to emulate them in lp_build_minify with float muls,
which should be way faster (saves over 20 instructions per 8-wide
lp_build_minify). This wouldn't work for "generic" 32bit shifts though
since we've got only 24bits of mantissa (actually for left shifts it would
work by using sse41 int mul instead of float mul but not for right shifts).
Note that this has very limited scope for now, since this is only used with
per-pixel lod (otherwise we're avoiding the non-constant shift count by doing
per-quad shifts manually), and only 1d textures even then (though the latter
should change).
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7df7e730fb71249993c9dcabff4b5e7075a775f6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 1 14:56:53 2013 -0700
nouveau: Use _NEW_SCISSOR instead of hooking through dd_function_table
This will enable removing the dd_function_table::Scissor hook in the
near future.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f30425424dee72c76df4195da24df8ef913af56
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 1 14:56:28 2013 -0700
nouveau: Use _NEW_VIEWPORT instead of hooking through dd_function_table
This will enable removing the dd_function_table::DepthRange hook in the
near future.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a5b84cece17d4cacb699b8fd47080925228ca9a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 1 11:40:44 2013 -0700
radeon / r200: Don't pass unused parameters to radeon_viewport
The x, y, width, and height parameters aren't used by radeon_viewport,
so don't pass them. This should make future changes to the
dd_function_table::Viewport interface a little easier.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jljusten at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Cc: Courtney Goeltzenleuchter <courtney at lunarg.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=619a9bee7da9f3b8271841b6782dfc846dd7ee32
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 1 11:38:25 2013 -0700
i915: Bring sanity to the Viewport function
The i830 and the i915 driver have the same dd_function_table::Viewport
function... it just has two names and lives in two places. Using a
single implementation allows cleaning up the saved_viewport nonsense
too.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jljusten at gmail.com>
Cc: Courtney Goeltzenleuchter <courtney at lunarg.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=abd962f1d5e0991073312305560516a3e64ef1cb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 1 11:36:47 2013 -0700
i965: Eliminate the saved_viewport wrapper
The i965 driver never installed a dd_function_table::Viewport function,
so this wrapper never actually did anything.
No piglit regressions on IVB on DRI2.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jljusten at gmail.com>
Cc: Courtney Goeltzenleuchter <courtney at lunarg.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c7605685d2b8250b92acf5ce8f6f217bb3f1a12
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Tue Nov 5 01:31:26 2013 +0000
mesa: Remove last BEOS checks
* Goodbye BeOS, we hardly knew thee
* As BeOS was gcc2 only, there was little chance
of this being useful.
* Doesn't effect Haiku in any meaningful way
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c883ee449882a580088deac7b4706f502ef0f33c
Author: José Fonseca <jfonseca at vmware.com>
Date: Fri Oct 25 12:39:42 2013 +0100
util/u_format: take normalized flag in consideration in util_format_is_rgba8_variant
Just happened to notice it was missing while looking at it.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=86cdff56353a223d3c9c1cd24bc83a1799eaa6d9
Author: Paul Berry <stereotype441 at gmail.com>
Date: Wed Oct 30 17:01:01 2013 -0700
glsl: Don't generate misleading debug names when packing gs inputs.
Previously, when packing geometry shader input varyings like this:
in float foo[3];
in float bar[3];
lower_packed_varyings would declare a packed varying like this:
(declare (shader_in flat) (array ivec4 3) packed:foo[0],bar[0])
That's confusing, since the packed varying acutally stores all three
values of foo and all three values of bar.
This patch causes it to generate the more sensible declaration:
(declare (shader_in flat) (array ivec4 3) packed:foo,bar)
Note that there should be no functional change for users of geometry
shaders, since the packed name is only used for generating debug
output. But this should reduce confusion when using INTEL_DEBUG=gs.
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=749cb8909714fed57b0213f4ad92def3bb24f153
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sun Nov 3 20:27:13 2013 -0800
gallivm: Remove llvm::DisablePrettyStackTrace for LLVM >= 3.4.
LLVM 3.4 r193971 removed llvm::DisablePrettyStackTrace and made the
pretty stack trace opt-in rather than opt-out.
The default value of DisablePrettyStackTrace has changed to true in LLVM
3.4 and newer.
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60929
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e759f1c111018949db114e76ebf1a723525fb802
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Mon Nov 4 18:51:41 2013 +0000
target/haiku-softpipe: Fix viewport issues
* Call mesa viewport call on winndow resize
* Add initial postprocessing code
* Pass hgl_context to private statetracker
as it is more useful than GalliumContext
* Use Lock and Unlock functions to standardize
GalliumContext locking
* Create texture resources in texture validation
Acked-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=faaf568cfb0548d6162d6fefd68f6ad62eb6406c
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 18:07:37 2013 -0700
mesa: remove __alpha__ && CCPML check
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2671b576b22614d1b424a1fe70f84ee6c3920d13
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 17:47:19 2013 -0700
mesa: remove OPENSTEP stuff
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=32577fc0adec86557c53ced8fb13dd5de76e58e0
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 17:47:19 2013 -0700
mesa: remove macintosh preprocessor stuff
IIRC, this is MacOS 9.x stuff.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a5d2d2db806629d635b72708293c01148f6c1d3
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 17:47:19 2013 -0700
mesa: remove __QUICKDRAW__ tests
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bdc94b94db18f14725a3ea9d2a9ebe0af1c13fd
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 17:47:19 2013 -0700
mesa: remove WGLAPI macro
WGLAPI was defined in glheader.h but wasn't used anywhere.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b4b94a9567b7322e2ef6e28dcd38a23374684ea
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 13:29:37 2013 -0700
i965: Expose brw_reg_from_fs_reg() to other files.
This will be useful for Broadwell code as well.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10cb91d7fba822a13fbdc1ad12f76b545d4e302b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 16:21:01 2013 -0700
i965: Combine gen6_clip_state.c and gen7_clip_state.c.
The changes between Gen6-7 are minimal, and can easily be solved with
an extra generation check. This cuts a lot of duplicated code.
It also helps prevent even more duplication for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67b8f4c569030a2b6392560f8e73283a6a73dc7e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Nov 4 11:58:10 2013 -0800
dri/nouveau: Fix nouveau_init_screen2 breakage.
Fix incorrect init ordering in nouveau_init_screen2 caused by
083f66fdd6451648fe355b64b02b29a6a4389f0d.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71172
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=35fe7ed7d3c45f5263ae42bcedecc00ba6adf91d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 1 11:29:13 2013 -0700
i965/gen7: Add instruction latency estimates for untyped atomics and reads.
The latency information has been obtained empirically from
measurements taken on Haswell and Ivy Bridge.
Acked-by: Paul Berry <stereotype441 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba885c30c74f9efc94743d4582d30a0e70924b97
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Sep 25 16:31:35 2013 -0700
i965/gen7: Handle atomic instructions from the VEC4 back-end.
This can deal with all the 15 32-bit untyped atomic operations the
hardware supports, but only INC and PREDEC are going to be exposed
through the API for now.
v2: Represent atomics as GLSL intrinsics. Add support for variably
indexed atomic counter arrays.
v3: Add comment on why we don't need to assign uniform storage for
atomic counters.
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=764f40d92edfdfea4ea2b092fd1ba7888cc7ea7e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Sep 25 16:30:20 2013 -0700
i965/gen7: Handle atomic instructions from the FS back-end.
This can deal with all the 15 32-bit untyped atomic operations the
hardware supports, but only INC and PREDEC are going to be exposed
through the API for now.
v2: Represent atomics as GLSL intrinsics. Add support for variably
indexed atomic counter arrays. Fix interaction with fragment
discard.
v3: Add comment on why we don't need to assign uniform storage for
atomic counters.
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34fe051e215107dddbaae71e2edf15f88d839936
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Oct 20 14:02:08 2013 -0700
i965: Add a 'has_side_effects' back-end instruction predicate.
This patch fixes the three dead code elimination passes and the
VEC4/FS instruction scheduling passes so they leave instructions with
side effects alone.
At some point it might be interesting to have the instruction
scheduler calculate the exact memory dependencies between atomic ops,
but they're rare enough that it seems unlikely that it will make any
practical difference.
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf045bf9b409c47019fa7d9c859eaf8d50dd7032
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Nov 4 11:26:13 2013 -0800
clover: Calculate optimal work group size when it's not specified by the user.
Inspired by a patch sent to the mailing list by Tom Stellard, but
using a different algorithm to calculate the optimal block size that
has been found to be considerably more effective.
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67a303744434c9129931e9627d97e34af6bef8f3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Nov 4 11:24:10 2013 -0800
clover: Constify some command_queue arguments.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e9206bdccda628682204fa0b35b2bf698d64295
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Oct 30 11:11:06 2013 -0700
clover: Workaround compiler bug present in GCC 4.7.0-4.7.2.
Variadic template aliases make these versions of GCC very confused,
write down the full type spec instead.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a2bdbb76f9fecf34c6b5fb39b60fda745440e4f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 1 16:44:10 2013 +0000
st/xorg: handle updates to DamageUnregister API
xserver 1.14.99.2 simplified the DamageUnregister API, by
dropping the drawable argument.
Follow xf86-video-intel and xf86-video-vmware approach and
handle the new API by checking XORG_VERSION_CURRENT.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71110
Reported-by: Michał Górny <mgorny at gentoo.org>
Reported-by: Vinson Lee <vlee at freedesktop.org>
Tested-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e0ed59959ad38b9dd469d9924e6794c8d21abcf
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 07:33:41 2013 -0700
mesa: remove Watcom C support
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a1f74e7d93c8c1e7fa46784ea0bdb6c7bd47100
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 07:26:54 2013 -0700
mesa: remove Centerline C support from gl.h
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61ec037c61de3e068250e530ac073c2b0f250a1b
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 07:29:57 2013 -0700
mesa: remove BUILD_FOR_SNAP bits
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d5d63d63c882de3437df67caa4733430db7116d
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 4 07:25:22 2013 -0700
mesa: remove SciTech stuff from gl.h
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6463b94973912c2c7f056132e8744db0dc98c6b8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Nov 3 20:27:28 2013 +0100
r600g: properly unbind a DSA state being deleted in r600_delete_dsa_state
Tested-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0733479f06c0e6d6b36b863982329455aaf39af
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 31 15:49:36 2013 +0100
docs/GL3: document radeonsi support, minor cleanup
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a767f57a7d755944a3f3db853767cac727ae761a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 31 15:20:06 2013 +0100
radeonsi: implement ARB_vertex_type_2_10_10_10_rev
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a250877eaea932e2bddd35ba694e4dc38cc57cc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 31 15:32:30 2013 +0100
r600g,radeonsi: properly expose texture buffer formats
This exposes GL_ARB_texture_buffer_object_rgb32.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbeedbb7ab47398b67a10c6ab81acd1bec6f0edd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 31 15:08:49 2013 +0100
radeonsi: implement texture buffer objects
GLSL 1.40 is done.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=164de0d2a5d4e102beba4f7a716516a5e76ac868
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 30 21:44:07 2013 +0100
radeonsi: report our border color behavior
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4569bf919930a417d9d94f0d626d88ed164b32a9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 30 20:44:23 2013 +0100
radeonsi: bind a dummy constant buffer in place of NULL buffers
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fd42001231b70ba1764b1455d642037d2d5fff5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 25 11:45:47 2013 +0200
radeonsi: implement uniform buffer objects
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0cf73a4086e2ef256f6a21c4e30030cc07fc5b6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 30 14:24:27 2013 +0100
tgsi/scan: set maximum index for each constant buffer
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5f0080d912d9231773a087c9f3e3a55136c467a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 30 00:36:58 2013 +0100
radeonsi: try to fix IA_MULTI_VGT_PARAM programming
This doesn't make any difference on Bonaire, but it might help on Hawaii.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e438194757fb7e013ea039dfddd75ae469d8164
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 30 00:22:01 2013 +0100
winsys/radeon: use type-3 NOPs for CS padding on CIK
The type-2 NOPs are said to be unstable. It doesn't make a difference here.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b2c6cd205bc35f0409ccf055a77e8ca6eab0db3
Author: Aaron Watry <awatry at gmail.com>
Date: Fri Nov 1 10:25:43 2013 -0500
clover: fix build with LLVM 3.4
dso_list was added as an argument for createInternalizePass in 3.4, and then
it was removed again in the same llvm version.
Tested-by: Mike Lothian <mike at fireburn.co.uk>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fc41e2eeaad556810d68cc623a52ea551b9d907
Author: Brian Paul <brianp at vmware.com>
Date: Fri Nov 1 17:07:55 2013 -0600
draw: move type construction out of loop
We can create clip_ptr_type once instead of n times inside the loop.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f896627175384fd5943f21804700a155ba4e8a0
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Sun Nov 3 13:14:50 2013 -0800
i965: Add driconf option clamp_max_samples
The new option clamps GL_MAX_SAMPLES to a hardware-supported MSAA mode.
If negative, then no clamping occurs.
v2: (for Paul)
- Add option to i965 only, not to all DRI drivers.
- Do not realy on int->uint cast to convert negative
values to large positive values. Explicitly check for
clamp_max_samples < 0.
v3: (for Ken)
- Don't allow clamp_max_samples to alter context version.
- Use clearer for-loop and correct comment.
- Rename variables.
v4: (for Ken)
- Merge identical if-branches.
Reviewed-and-tested-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=68f1b274b06ed6f14cc8d069bee3cabc520fb553
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sun Nov 3 14:43:53 2013 -0800
i965: Fix logic_op check.
Fixes "Macro compares unsigned to 0" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9943b6612b875286ab183c17e6ba89e2eafc77ab
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sun Nov 3 14:42:18 2013 -0800
i915: Fix logic_op check.
Fixes "Macro compares unsigned to 0" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=14ddc8334698d74e28288fe16fe83ffd62c80a1a
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sat Oct 26 00:10:25 2013 -0700
i965: Initialize vec4_visitor member variables.
Fixes "Uninitialized pointer field" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa8b1514d31d1ffb3d9e2a208ac7d1bd774754b2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 2 12:20:29 2013 +0100
gallium/targets: remove vdpau-softpipe
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c2531847fba8c8eaac287936a20dc07612d4b59
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 2 12:18:44 2013 +0100
gallium/targets: remove xvmc-softpipe
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e17c12fa7b2ceb6a7a77ed36604e0c3fd818db3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 2 12:07:42 2013 +0100
gallium/targets: remove r300/vdpau
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f7233c8ea7f5fd9893cf539d2e216b0bc3cffa8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 2 12:03:42 2013 +0100
gallium/targets: remove r300/xvmc
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=be331e82d12e37a0e7baea96cc9f4356ead992ea
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Nov 1 19:42:47 2013 +0100
gallium/targets: remove radeonsi/xorg
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da82d7b6ba0c7e2e2d576c58fea4fbfa132511cb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Nov 1 19:36:12 2013 +0100
gallium/targets: remove r600/xorg
Reviewed-by: Christian König <christian.koenig at amd.com>
More information about the mesa-commit
mailing list