Mesa (broadwell): 65 new commits
Kenneth Graunke
kwg at kemper.freedesktop.org
Tue Nov 12 01:09:12 UTC 2013
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2d157c86cabf5a5b71b953dc550ca057ff73977
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 8 22:21:56 2013 -0800
i965: Fix up PIPE_CONTTROL packets for Broadwell?
I believe these need to grow by 1 DWord for the AddressHigh bits.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a903d698bd3a4699386a2ce676a4f65e557e41b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 8 22:21:29 2013 -0800
i965: Disable workaround flush for push constants on Broadwell.
If it wasn't necessary for Haswell, it's likely not to be necessary for
Broadwell either.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ca3ad8280597b256406c16013d992c0ba4e7cf3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 8 21:58:35 2013 -0800
i965: Emit HIER_DEPTH_BUFFER too
this depth buffer code is crap
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d5a8d16fedc148e301a638937fd29767a027394
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:41:34 2013 -0700
i965: Add Broadwell PCI IDs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40bc368b75fe087012cb9f80a21bd1e43c0ec624
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 23:19:55 2013 -0800
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes:
- 48-bit relocations
- Thread count is specified as U/2-1 instead of U-1.
- An extra DWord (DW9) with clip planes, URB entry output length/offsets
- We need to program the "Expected Vertex Count" (VerticesIn)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9da42034db67d519bb720a15a078ea2314034c93
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 16:12:50 2013 -0800
more SOL updates...for XFB2/3/instanced
XXX: Need to store {0, 0, 0, 0} in offset_bo at beginXFB time.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ba270fa04d83ffe269187a833dc6c2d1fb458bd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 14:09:07 2013 -0800
i965: Skip the register write check on Broadwell.
MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code
doesn't work. But supposedly Broadwell has a register whitelist and
just works out of the box anyway, so there's no need to check.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bb273308c33ae9e8b1d76f0f9ee9fd2d73c0c54
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:20:37 2012 -0800
i965: Update multisampling state for Broadwell.
On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x). It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.
Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN. With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.
Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7. This patch, however, does not implement 2x
and 16x.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=870c50e49669f2865cd51cdd46ecf3ddc4355686
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 22 12:20:31 2013 -0800
i965: Fix texture border color on Broadwell.
The Gen7 sampler state code still works. Increasing the alignment to
64 bytes makes bit 5 zero, which is good because it's now reserved.
Since we don't use the new filter bits, we can leave those as zero too,
which means we don't need to update the code to update the pointer.
(We probably should anyway, for clarity, but alas, another day.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2c19cd2ca72eba2dc3616dfe4bf3bb5aeaf5788
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jan 20 08:58:14 2013 -0800
i965: Don't use MACH for integer multiplies on Gen8+.
The documentation is really hard to follow, but apparently a 32-bit x
32-bit multiply just works without the MACH macro. The macro apparently
is only necessary to get the full 64-bit value.
Fixes Piglit tests [vf]s-op-mult-int-int.shader_test.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9032a2c5901aa497f50c862e89572e3af68a8ca4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 14 21:43:28 2013 -0800
i965: Fix texture swizzling on Broadwell.
Like Haswell, we do this in SURFACE_STATE rather than shader
workarounds.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=542d31f66b5055999dc06ff829249eb09a85ccd6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 12 16:12:38 2013 -0800
i965: Workaround 64-bit relocations in blitter code.
Emit zeros for the high 16 bits of each address. This is not what we
want long term, but gets things working for now.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e3849278567e5d7a315e9c26d037dd1451aabcd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 03:58:30 2012 -0800
i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.
(This patch was written before Paul's refactor to reuse
brw_emit_depthbuffer and just implement a gen7_emit_depth_stencil_hiz
function. We should probably rearchitect it to fit that new model, as
it's much better. --Ken)
(The rest of this commit message was written by Chad.)
The depth buffer packet emitted by this patchis incomplete.
We must use the packet's level/layer fields to specify the miptree slice
into which to render. This patch emits 0 there, and hence all rendering
occurs to the miptree's base slice. (In gen5 through gen7, we used the
intra-tile x/y offsets to specify the miptree slice. But gen8 removed
those fields.)
However, the incomplete implementation does show some signs of life. It
fixes the page fault in piglit:fbo-depth. (The test's segfault was
likely due to the high 16 bits of the surface base address being
invalid).
v2: [chadv]
- Comment in patch that depth buffer packet needs level/layer
fields.
- Remove comments specific to gen7.
- Expand commit message.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=002604180ed6ad7a8909cb107c9059f5fb159003
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 19:30:26 2012 -0800
i965: Update BLEND_STATE for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c2e8a4cd77c692290f48decea28f66d76820641
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 15:34:34 2012 -0800
i965: Update SF_CLIP_VIEWPORT for Broadwell.
It has more fields now. Not sure if this is correct for render_to_fbo.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e79197431dc4445166e1410f441c9bd62ae48ae
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Dec 15 01:14:03 2012 -0800
i965: Set vertical alignment unit to 4 on Broadwell.
Broadwell doesn't support a surface vertical alignment of 2. It only
supports VALIGN_4, VALIGN_8, or VALIGN_16. I chose 4 since it's the
least wasteful.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0af1de70b366e951cbe5ef52400846bd68ce6bf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 16:39:03 2012 -0800
i965: Rework SURFACE_STATE entries for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b50e626d0a4e77dc6dcd930d019cf8ac57bce285
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 14:45:19 2012 -0800
i965: Update SOL state for Broadwell.
Unlike on Gen7, we can directly set the offset via the state packet.
We also -have- to: the kernel SOL reset code won't work anymore.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e561c09b99fef7418b60625850118f16fb690612
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:39:19 2012 -0800
i965: Update the code that disables unused shader stages for Broadwell.
This may or may not be necessary, but it shouldn't hurt.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4925692459f8452769b6472b19712a4c16f48baf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 11:39:14 2012 -0800
i965: Double the push constant space multipliers on Broadwell too.
Broadwell has 2Kb push constant size increments like Haswell GT3.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a632994685cc405742534d278a871752c93d9bc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 16:29:33 2013 -0700
i965: Update 3DSTATE_CLIP for Broadwell.
Broadwell doesn't have GEN6_CLIP_Z_TEST, and doesn't make you specify
the polygon winding information (it pulls that information from other
packets).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d5ef886971b9e1404ed71b9b610a992da435edd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 18:28:29 2012 -0800
i965: Rework vertex uploads for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fcca69ef3ff17573a5eed971764888897194c10
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:28:39 2012 -0800
i965: Update invariant state for Broadwell.
The only difference is that STATE_SIP takes a 48-bit address, so we need
to output two zeroes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40c91b1e071535fcd119e641af020bf2625b0130
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 13:53:40 2012 -0800
i965: Update STATE_BASE_ADDRESS for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4aaad4b5a820d1147475365ba5c3add5dba67732
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=223bae2031d8f61a4945351cffdf80ea6ab40d58
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:10:19 2012 -0800
i965: Rework 3DSTATE_VS for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e836dff3ac7c3214dae06a9fbd6c1f25d0e190a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 18:43:59 2012 -0800
i965: Add the new 3DSTATE_PS_BLEND state packet.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da3a568427712a1b71c945d6fdd7eea760483124
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 17:52:31 2012 -0800
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=38e495fd5c15a227d8f589b79f5c6e792dc79fe8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 14:37:33 2013 -0700
i965: Update SF, SBE, and RASTER state for Broadwell.
The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=190fcff007632f085fa766f104345739a87ec890
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 16:55:26 2013 -0800
i965: Introduce an OUT_RELOC64 macro.
Broadwell uses 48-bit addresses. The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.
Since individual buffers shouldn't be larger than 4GB in size, any
offsets into those buffers (buffer->offset + delta) should fit in the
low 32 bits. So I believe we can simply emit 0 for the high 16-bits,
and drm_intel_bo_emit_reloc() should patch it up.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9976da3f5e810275151e931eff09f988d2e714d0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:50:22 2012 -0800
i965: Bump generation assertions on workaround flushes.
These workaround flushes may not be necessary on Gen8. Investigation is
needed. Tentatively, let's do them out of caution.
v2: [chadv]
- Comment that flush may not be needed.
- Make assertion conditions symmetrical.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=550e29fbf3c29c39493f736e14829d7d9bdadfc2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:30:01 2012 -0800
i965: Use the Sandybridge VUE format on Broadwell as well.
It hasn't changed.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bcfcc0d4bd0069c862b2b365d66241f95509ff7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:16:18 2012 -0800
i965: Duplicate gen7_atoms to gen8_atoms.
It's going to diverge significantly. Starting out with a copy allows
future patches to change atoms one by one.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6f56608e6ce59ad4588102497041ca69dab9457
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 16 00:40:30 2012 -0800
i965/vs: Don't copy propagate into SEND-from-GRF messages.
SEND can't deal with swizzles, source modifiers, and so on. This should
avoid problems with VS pull constant loads on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=814c855fc91eeb459fb7042641f8294d8ef9596b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 16 00:02:43 2012 -0800
i965/vs: Always store pull constant offsets in GRFs on Gen8.
We need to SEND from a GRF, and we can only obtain those prior to
register allocation.
This allows us to do pull constant loads without the MRF hack.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41fed547616cbb67f62fd1bee03448e4e0cf9c67
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:38:26 2012 -0800
i965: Create a new fragment shader backend for Broadwell.
This replaces the old fs_generator backend.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c3dfd6c49f9d90281347fdb53c60ee21905c03a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:37:34 2012 -0800
i965: Create a new vec4 backend for Broadwell.
This replaces the old vec4_generator backend.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5843d7e9c9e1a2f342d506eb9d3680fd6a036b95
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:50 2012 -0800
i965: Add a new infrastructure for generating Broadwell shader assembly.
This replaces the brw_eu_emit.c layer for Broadwell. It will be
used by both the vector and scalar shader backends.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=37b2174fafbbd246c00ca9a4fbda3c18f85d3d66
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 11 00:26:11 2012 -0800
i965: Implement a disassembler for Broadwell's new instruction encoding
Heavily based on Keith Packard's existing brw_disasm.c code. I've tried
to go through most of the pieces (like SFIDs) and update the lists to
include features added in recent generations.
I had to use C++ since my new instruction representation requires it.
Unfortunately, C++98 doesn't allow the use of C99 array initializers,
which makes the arrays mapping values to strings harder to read. I
tried to compensate for this failing by adding additional comments.
The disassembly can definitely be improved, but this should at least
get INTEL_DEBUG=vs/fs working.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15c6b1b4d110bf13b3c636961a84e36fc6b1da28
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:26 2012 -0800
i965: Add a new representation for Broadwell shader instructions.
Broadwell significantly changes the EU instruction encoding. Many of
the fields got moved to different bit positions; some even got split
in two.
With so many changes, it was infeasible to continue using struct
brw_instruction. We needed a new representation.
This new approach is a bit different: rather than a struct, I created a
class that has four DWords, and helper functions that read/write various
bits. This has several advantages:
1. We can create several different names for the same bits. For
example, conditional modifiers, SFID for SEND instructions, and the
MATH instruction's function opcode are all stored in bits 27:24.
In each situation, we can use the appropriate setter function:
set_sfid(), set_math_function(), or set_cond_modifier(). This
is much easier to follow.
2. Since the fields are expressed using the original 128-bit numbers,
the code to create the getter/setter functions follows the table in
the documentation very closely.
To aid in debugging, I've enabled -fkeep-inline-functions when building
gen8_instruction.cpp. Otherwise, these functions cannot be called by
gdb, making it insanely difficult to print out anything.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a31e734de97e3915d3846006c91f7d18f52b5ea
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 5 16:55:06 2013 -0800
i965: Reserve space for "Vertex Count" in GS outputs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=30e424c092781064772ed547984adade80444baf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 13:35:15 2012 -0800
i965: Disable BLORP on Broadwell for now.
BLORP is essential. However, porting it to Gen8 is a huge amount of
work. Disabling it for now allows us to proceed with basic hardware
enablement.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9880eb5349108e4540c0574ba94b7da40b85a371
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 17:56:40 2012 -0800
i965: Disable HiZ on Broadwell for now.
HiZ is difficult to implement, and while it's essential for performance,
we don't need it right away for purposes of hardware enabling.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=817f3ee302fb1118f7a49983bb8b6529345e1714
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:45:47 2013 -0700
i965: Claim OpenGL 3.3 support on Broadwell.
Bugs aside, basically everything ought to work.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=376a9349e13599fe95c0e63feeb3d7a71a623d15
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:44:09 2013 -0700
i965: Add device info structs for Broadwell.
As always, the chipset limits here are placeholders, rather than the
actual values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0eee94c4a30f2ccef60cadcfe0e3f989951e623e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 14 21:26:28 2013 -0800
i965: Make swizzle_to_scs non-static.
We'll need this for Broadwell code as well.
Normally, when we make things public, we add the "brw" prefix. I'm not
crazy about that in this case, since it deals with prog_instruction.h's
SWIZZLE_XYZW values, rather than the BRW_SWIZZLE_XYZW enums. However,
I can't think of a better name, and at least the comments and code make
it clear.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=271ec2f266f7a39f2e98cf79eaf3305d81d7ba17
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 6 13:40:59 2013 -0800
i965: Move ud_reg_to_w() from brw_fs_generator.cpp to brw_reg.h.
This makes it available from other files, which will be useful for
Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbc0f54ecbf91cdf23dcd41782a2ca6f76bad8f3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 12:50:16 2013 -0700
i965: Move enum brw_urb_write_flags from brw_eu.h to brw_defines.h.
Broadwell code should not include brw_eu.h (since it is for Gen4-7
assembly encoding), but needs the URB write flags enum.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee374079894b61496bc1eb2ba8deb2e57e8df759
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 1 15:09:26 2013 -0800
i965/fs: Remove force_sechalf stack
Only Gen4 color write setup uses the force_sechalf flag, and it only
sets it on a single instruction. It also already has to get a pointer
to the instruction and manually set the saturate flag, so we may as well
just set force_sechalf the same way and avoid the complexity of a stack.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6a3fb69c6a0d993f111518f12b34dde3925c190
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 6 00:33:14 2013 -0800
i965: Use has_surface_tile_offset in depth/stencil alignment workaround.
Currently, has_surface_tile_offset is equivalent to gen == 4 && !is_g4x.
We already use it for related checks in brw_wm_surface_state.c, so it
makes sense to use it here too. It's simpler and more future-proof.
Broadwell also lacks surface tile offsets. With this patch, I won't
need to update any generation checking; I can simply not set the flag.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=110009302bddb4c42a5b3ed5ca451d6bb50a06a0
Author: Fabio Pedretti <fabio.ped at libero.it>
Date: Wed Nov 6 10:55:28 2013 +0100
gallium: fix build on GNU/kFreeBSD
Patch from Debian package
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Andreas Boll <andreas.boll.dev at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f4da81dc8a7060520baff82153330a9675f122a
Author: Fabio Pedretti <fabio.ped at libero.it>
Date: Wed Nov 6 10:55:27 2013 +0100
configure.ac: fix build on GNU/kFreeBSD
Based on existing patch from Debian package.
Debian bug: http://bugs.debian.org/524690
Reviewed-by: Andreas Boll <andreas.boll.dev at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d805c96eb991aae4bb325dc1b5f8ca0a7fb921c
Author: Fabio Pedretti <fabio.ped at libero.it>
Date: Tue Nov 5 16:51:19 2013 +0100
mesa: add arm64 support
Patch from Ubuntu package
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Andreas Boll <andreas.boll.dev at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da7daade92a4fb54c5cbb74ec6c2fba0ed895ff8
Author: Fabio Pedretti <fabio.ped at libero.it>
Date: Tue Nov 5 12:49:56 2013 +0100
r600/compute: silence unused var warning
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fd785ac49ffe85c62c6b7f515e2dcf9e9bbc5ca
Author: Paul Berry <stereotype441 at gmail.com>
Date: Mon Nov 4 18:48:17 2013 -0800
i965/gen6: Don't allow SIMD16 dispatch in 4x PERPIXEL mode with computed depth.
Hardware docs say we can only use SIMD8 dispatch in this condition.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e84f394e9bf9019cf088134e7cdafadb2187021
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Nov 5 11:21:53 2013 -0800
configure.ac: Drop no-out-of-tree notice.
We do support out of tree builds now.
Tested-by: Colin Walters <walters at verbum.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ca3926442361fb6e9ac75c7af63f37b94278ab7
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 4 14:52:22 2013 -0800
mesa: Build program as part of libmesa.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0bfb7c41ea0874d71530698ac9343936fc2e5bd
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 4 14:36:53 2013 -0800
mesa: Clean up use of top_srcdir/top_builddir.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8bc126cd37ff65773aec113956b8e442e595e630
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 4 16:26:29 2013 -0800
i965: Use unreachable() to silence a compiler warning.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a5223c24cc30b3d8698352782ad9130ee2407ae
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 4 16:24:35 2013 -0800
mesa: Add unreachable() macro.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b35ea0934933885b45348fb861d5ad9b8c284910
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Nov 6 15:40:25 2013 +0100
gallivm: fix indirect addressing of inputs
We weren't adding the soa offsets when constructing the indices
for the gather functions. That meant that we were always returning
the data in the first element.
(Copied straight from the same fix for temps.)
While here fix up a couple of broken comments in the fetch functions,
plus don't name a straight float type float4 which is just confusing.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Zack Rusin <zackr at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08556073d1fae993be4a30e34065af55efd1e0cd
Author: Vincent Lejeune <vljn at ovi.com>
Date: Mon Oct 21 21:05:57 2013 +0200
r600/llvm: Fix isampleBuffer on preEG
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1184f8fd34ac00fe4be495f00a4d2e0820eac153
Author: Vincent Lejeune <vljn at ovi.com>
Date: Mon Oct 21 18:48:21 2013 +0200
r600/llvm: Fix texbuf for pre EG gen
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36f1c6e3db6b8010ce4f06ed33e69f628b67e293
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 5 16:58:15 2013 -0700
mesa: for GLSL_DUMP_ON_ERROR, also dump the info log
Since it's helpful to know why the shader did not compile.
Also, call fflush() for Windows.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5580ff818e0559099ffc79af60872908e9d5d747
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Wed Nov 6 00:35:31 2013 +0100
st/vdpau: resolve delayed rendering for GL interop v2
Otherwise OutputSurface interop has funny results sometimes.
This fixes interop with the mpv media player.
v2 (chk): add proper locking
Signed-off-by: Christian König <christian.koenig at amd.com>
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