Mesa (9.2): i965: Also guard 3DSTATE_DRAWING_RECTANGLE with a flush in blorp.

[Carl Worth]

Module: Mesa
Branch: 9.2
Commit: 8c2e3c8275ae0f0ea01b35977ef0e577d86351d7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c2e3c8275ae0f0ea01b35977ef0e577d86351d7

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Oct 24 00:45:56 2013 -0700

i965: Also guard 3DSTATE_DRAWING_RECTANGLE with a flush in blorp.

Non-pipelined commands need this flush.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Xinkai Chen <yeled.nova at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Cc: "9.2" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 10a918e52c37715744f7980b2bc9da69575514da)

---

 src/mesa/drivers/dri/i965/gen6_blorp.cpp |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index a4a9081..04c0439 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -951,6 +951,9 @@ void
 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
                                   const brw_blorp_params *params)
 {
+   if (brw->gen == 6)
+      intel_emit_post_sync_nonzero_flush(brw);
+
    BEGIN_BATCH(4);
    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
    OUT_BATCH(0);