Mesa (broadwell): 46 new commits
Kenneth Graunke
kwg at kemper.freedesktop.org
Wed Nov 13 01:47:28 UTC 2013
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4babc50adbf17b5df2e4d304d0b8b4a1d357f552
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:41:34 2013 -0700
i965: Add Broadwell PCI IDs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bec8fb33bdf4d826aaaafe85c6bbcb9edeebd5e3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 23:19:55 2013 -0800
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes:
- 48-bit relocations
- Thread count is specified as U/2-1 instead of U-1.
- An extra DWord (DW9) with clip planes, URB entry output length/offsets
- We need to program the "Expected Vertex Count" (VerticesIn)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=704412fb1f1c08399212dfcc8c58fd9bcc6fb337
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 16:12:50 2013 -0800
more SOL updates...for XFB2/3/instanced
XXX: Need to store {0, 0, 0, 0} in offset_bo at beginXFB time.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=895c5bb0468fa295d89307f3ec500342742a28eb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 14:09:07 2013 -0800
i965: Skip the register write check on Broadwell.
MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code
doesn't work. But supposedly Broadwell has a register whitelist and
just works out of the box anyway, so there's no need to check.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbb834d2160c3e5b7864a305bbf06203e47dff66
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:20:37 2012 -0800
i965: Update multisampling state for Broadwell.
On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x). It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.
Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN. With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.
Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7. This patch, however, does not implement 2x
and 16x.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0bcbd279f11c95d9d712b4d0dc16394991a904dc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 22 12:20:31 2013 -0800
i965: Fix texture border color on Broadwell.
The Gen7 sampler state code still works. Increasing the alignment to
64 bytes makes bit 5 zero, which is good because it's now reserved.
Since we don't use the new filter bits, we can leave those as zero too,
which means we don't need to update the code to update the pointer.
(We probably should anyway, for clarity, but alas, another day.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=037db845ec5e792d05b006df89d2dd48b3502122
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jan 20 08:58:14 2013 -0800
i965: Don't use MACH for integer multiplies on Gen8+.
The documentation is really hard to follow, but apparently a 32-bit x
32-bit multiply just works without the MACH macro. The macro apparently
is only necessary to get the full 64-bit value.
Fixes Piglit tests [vf]s-op-mult-int-int.shader_test.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=04f485ad4ccd4f42a459a23035c6964230295770
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 14 21:43:28 2013 -0800
i965: Fix texture swizzling on Broadwell.
Like Haswell, we do this in SURFACE_STATE rather than shader
workarounds.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f01568e106efc112833891e4a4ed33bbd690e0df
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 12 16:12:38 2013 -0800
i965: Workaround 64-bit relocations in blitter code.
Emit zeros for the high 16 bits of each address. This is not what we
want long term, but gets things working for now.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23332457976f4c6bbe9b2e79bb6b26ce19e8c780
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 03:58:30 2012 -0800
i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.
(This patch was written before Paul's refactor to reuse
brw_emit_depthbuffer and just implement a gen7_emit_depth_stencil_hiz
function. We should probably rearchitect it to fit that new model, as
it's much better. --Ken)
(The rest of this commit message was written by Chad.)
The depth buffer packet emitted by this patchis incomplete.
We must use the packet's level/layer fields to specify the miptree slice
into which to render. This patch emits 0 there, and hence all rendering
occurs to the miptree's base slice. (In gen5 through gen7, we used the
intra-tile x/y offsets to specify the miptree slice. But gen8 removed
those fields.)
However, the incomplete implementation does show some signs of life. It
fixes the page fault in piglit:fbo-depth. (The test's segfault was
likely due to the high 16 bits of the surface base address being
invalid).
v2: [chadv]
- Comment in patch that depth buffer packet needs level/layer
fields.
- Remove comments specific to gen7.
- Expand commit message.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4356e1dd886e62acc0f58aaff9a087ce31525ae9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 19:30:26 2012 -0800
i965: Update BLEND_STATE for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61f6bd6a832c52ec519874bde11527aa042d2689
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 15:34:34 2012 -0800
i965: Update SF_CLIP_VIEWPORT for Broadwell.
It has more fields now. Not sure if this is correct for render_to_fbo.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e8dd009cea68ab2ab9f7ced37599b59e537b729
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Dec 15 01:14:03 2012 -0800
i965: Set vertical alignment unit to 4 on Broadwell.
Broadwell doesn't support a surface vertical alignment of 2. It only
supports VALIGN_4, VALIGN_8, or VALIGN_16. I chose 4 since it's the
least wasteful.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=675a8f8dd226144bf5f25b07b1b1bb4518e2c3c0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 16:39:03 2012 -0800
i965: Rework SURFACE_STATE entries for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2a60a11e2b4b942b714b23eb03365efe262c452
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 14:45:19 2012 -0800
i965: Update SOL state for Broadwell.
Unlike on Gen7, we can directly set the offset via the state packet.
We also -have- to: the kernel SOL reset code won't work anymore.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f46738af5cba5df2988f02970cd5a1e839ecfa7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:39:19 2012 -0800
i965: Update the code that disables unused shader stages for Broadwell.
This may or may not be necessary, but it shouldn't hurt.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01c8e6a097995bc70628972063ea97ae442ac48c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 11:39:14 2012 -0800
i965: Double the push constant space multipliers on Broadwell too.
Broadwell has 2Kb push constant size increments like Haswell GT3.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea7c5ac022560a744b227dd2a68d751ab9636a1c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 16:29:33 2013 -0700
i965: Update 3DSTATE_CLIP for Broadwell.
Broadwell doesn't have GEN6_CLIP_Z_TEST, and doesn't make you specify
the polygon winding information (it pulls that information from other
packets).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=86d853464249fbfe011ba89da0fa48a1900b7577
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 18:28:29 2012 -0800
i965: Rework vertex uploads for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cc1b7f0efc032d6dc82c77e280610c33ace5bb9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:28:39 2012 -0800
i965: Update invariant state for Broadwell.
The only difference is that STATE_SIP takes a 48-bit address, so we need
to output two zeroes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9cc2c0f26f8c6d2dd0dab37d16bb0e0f6c9d156f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 13:53:40 2012 -0800
i965: Update STATE_BASE_ADDRESS for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea07d8d5eace0877c251aeab1ab3c3505c5cb3ad
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f83979d8945a136cc11c020fc425ef5cace78b5b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:10:19 2012 -0800
i965: Rework 3DSTATE_VS for Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7f981a4ebd41e786638572e89c5ef274ee64b39
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 18:43:59 2012 -0800
i965: Add the new 3DSTATE_PS_BLEND state packet.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a7e8a4718514be5161d1406d47910c24efea9ef
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 17:52:31 2012 -0800
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d6abaf45482879ccc88ed67384bd4c06a689fe4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 14:37:33 2013 -0700
i965: Update SF, SBE, and RASTER state for Broadwell.
The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f746cbc23b364b60dff6c2566eddd816f2f8410a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 16:55:26 2013 -0800
i965: Introduce an OUT_RELOC64 macro.
Broadwell uses 48-bit addresses. The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.
Since individual buffers shouldn't be larger than 4GB in size, any
offsets into those buffers (buffer->offset + delta) should fit in the
low 32 bits. So I believe we can simply emit 0 for the high 16-bits,
and drm_intel_bo_emit_reloc() should patch it up.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ba5ec8c1f7734975caada6e0361f55b7ec8b905
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:50:22 2012 -0800
i965: Bump generation assertions on workaround flushes.
These workaround flushes may not be necessary on Gen8. Investigation is
needed. Tentatively, let's do them out of caution.
v2: [chadv]
- Comment that flush may not be needed.
- Make assertion conditions symmetrical.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f340980a49450bc9e4b95d0b4405958aa7704d6a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:30:01 2012 -0800
i965: Use the Sandybridge VUE format on Broadwell as well.
It hasn't changed.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b0625492689b6034900a6d2ad1e86665e699a81
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:16:18 2012 -0800
i965: Duplicate gen7_atoms to gen8_atoms.
It's going to diverge significantly. Starting out with a copy allows
future patches to change atoms one by one.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9af2042b88d4195a9a833f38e5bad56607a8f0c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 16 00:40:30 2012 -0800
i965/vs: Don't copy propagate into SEND-from-GRF messages.
SEND can't deal with swizzles, source modifiers, and so on. This should
avoid problems with VS pull constant loads on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9a2c22dfc08146b8f153e1134a610e5ed2c6a95
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 16 00:02:43 2012 -0800
i965/vs: Always store pull constant offsets in GRFs on Gen8.
We need to SEND from a GRF, and we can only obtain those prior to
register allocation.
This allows us to do pull constant loads without the MRF hack.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1867f0c8f5f1b3ebe7aec3fd5c5c4a17a4987c5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:38:26 2012 -0800
i965: Create a new fragment shader backend for Broadwell.
This replaces the old fs_generator backend.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75e3eee692f8a37eca6d07f963db911e9173782f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:37:34 2012 -0800
i965: Create a new vec4 backend for Broadwell.
This replaces the old vec4_generator backend.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=88468945b5f104ebb0560b9659a35caaa0806144
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:50 2012 -0800
i965: Add a new infrastructure for generating Broadwell shader assembly.
This replaces the brw_eu_emit.c layer for Broadwell. It will be
used by both the vector and scalar shader backends.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6340d33f64b72744cebac5cea528fad7cc361695
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 11 00:26:11 2012 -0800
i965: Implement a disassembler for Broadwell's new instruction encoding
Heavily based on Keith Packard's existing brw_disasm.c code. I've tried
to go through most of the pieces (like SFIDs) and update the lists to
include features added in recent generations.
I had to use C++ since my new instruction representation requires it.
Unfortunately, C++98 doesn't allow the use of C99 array initializers,
which makes the arrays mapping values to strings harder to read. I
tried to compensate for this failing by adding additional comments.
The disassembly can definitely be improved, but this should at least
get INTEL_DEBUG=vs/fs working.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db284fe33908f00f55591c8f4e7a79f3caf2d7ca
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:26 2012 -0800
i965: Add a new representation for Broadwell shader instructions.
Broadwell significantly changes the EU instruction encoding. Many of
the fields got moved to different bit positions; some even got split
in two.
With so many changes, it was infeasible to continue using struct
brw_instruction. We needed a new representation.
This new approach is a bit different: rather than a struct, I created a
class that has four DWords, and helper functions that read/write various
bits. This has several advantages:
1. We can create several different names for the same bits. For
example, conditional modifiers, SFID for SEND instructions, and the
MATH instruction's function opcode are all stored in bits 27:24.
In each situation, we can use the appropriate setter function:
set_sfid(), set_math_function(), or set_cond_modifier(). This
is much easier to follow.
2. Since the fields are expressed using the original 128-bit numbers,
the code to create the getter/setter functions follows the table in
the documentation very closely.
To aid in debugging, I've enabled -fkeep-inline-functions when building
gen8_instruction.cpp. Otherwise, these functions cannot be called by
gdb, making it insanely difficult to print out anything.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc36b0cc3b3aaed26253f8612c3005dfbf6a4af2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 5 16:55:06 2013 -0800
i965: Reserve space for "Vertex Count" in GS outputs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=48b8b7adc5b9142397d54d3a4d307366b413bbe5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 13:35:15 2012 -0800
i965: Disable BLORP on Broadwell for now.
BLORP is essential. However, porting it to Gen8 is a huge amount of
work. Disabling it for now allows us to proceed with basic hardware
enablement.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fc63d0037c8fa5a48e6f49152f342556e1e6f36
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 17:56:40 2012 -0800
i965: Disable HiZ on Broadwell for now.
HiZ is difficult to implement, and while it's essential for performance,
we don't need it right away for purposes of hardware enabling.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64cd26cda6b389dddadf98d462b002a46eee5ad6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:45:47 2013 -0700
i965: Claim OpenGL 3.3 support on Broadwell.
Bugs aside, basically everything ought to work.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=082f94e9cae2aad5f040bef36990907c9d69c13b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:44:09 2013 -0700
i965: Add device info structs for Broadwell.
As always, the chipset limits here are placeholders, rather than the
actual values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=05c94d71c4eab2838b925ea85778d44a21e18bdc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 14 21:26:28 2013 -0800
i965: Make swizzle_to_scs non-static.
We'll need this for Broadwell code as well.
Normally, when we make things public, we add the "brw" prefix. I'm not
crazy about that in this case, since it deals with prog_instruction.h's
SWIZZLE_XYZW values, rather than the BRW_SWIZZLE_XYZW enums. However,
I can't think of a better name, and at least the comments and code make
it clear.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ea645d747597daae1da4f66a48af441bc2967f7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 12:50:16 2013 -0700
i965: Move enum brw_urb_write_flags from brw_eu.h to brw_defines.h.
Broadwell code should not include brw_eu.h (since it is for Gen4-7
assembly encoding), but needs the URB write flags enum.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=22b8bb443e31b04de00e5e64043160bcaff4ea24
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 1 15:09:26 2013 -0800
i965/fs: Remove force_sechalf stack
Only Gen4 color write setup uses the force_sechalf flag, and it only
sets it on a single instruction. It also already has to get a pointer
to the instruction and manually set the saturate flag, so we may as well
just set force_sechalf the same way and avoid the complexity of a stack.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0155167b91ff67bdda430ba3a3ee8ffb9a8e2da
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 6 00:33:14 2013 -0800
i965: Use has_surface_tile_offset in depth/stencil alignment workaround.
Currently, has_surface_tile_offset is equivalent to gen == 4 && !is_g4x.
We already use it for related checks in brw_wm_surface_state.c, so it
makes sense to use it here too. It's simpler and more future-proof.
Broadwell also lacks surface tile offsets. With this patch, I won't
need to update any generation checking; I can simply not set the flag.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
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