Mesa (master): i965: Weaken the flushing in gen7_end_transform_feedback().
Kenneth Graunke
kwg at kemper.freedesktop.org
Sat Oct 26 05:25:45 UTC 2013
Module: Mesa
Branch: master
Commit: d07d38e696ef4a472910a6abe06b8b8dde4acbbc
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d07d38e696ef4a472910a6abe06b8b8dde4acbbc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon May 27 19:18:14 2013 -0700
i965: Weaken the flushing in gen7_end_transform_feedback().
Since 062317d6671 (i965: Go back to using the kernel SOL reset feature.)
we've been flushing the batch on BeginTransformFeedback(). So it's not
necessary to do it on EndTransformFeedback(). A PIPE_CONTROL will work.
This makes gen7_end_transform_feedback() exactly the same as the gen6
variant. However, they'll diverge again shortly.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
---
src/mesa/drivers/dri/i965/gen7_sol_state.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index ec46b56..abfe0a0 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -263,13 +263,13 @@ void
gen7_end_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj)
{
- /* Because we have to rely on the kernel to reset our SO write offsets, and
- * we only get to do it once per batchbuffer, flush the batch after feedback
- * so another transform feedback can get the write offset reset it needs.
- *
- * This also covers any cache flushing required.
+ /* After EndTransformFeedback, it's likely that the client program will try
+ * to draw using the contents of the transform feedback buffer as vertex
+ * input. In order for this to work, we need to flush the data through at
+ * least the GS stage of the pipeline, and flush out the render cache. For
+ * simplicity, just do a full flush.
*/
struct brw_context *brw = brw_context(ctx);
- intel_batchbuffer_flush(brw);
+ intel_batchbuffer_emit_mi_flush(brw);
}
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