Mesa (master): i965: Enable INTDIV in SIMD16 mode.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: c66d928f2c9fa59e162c391fbdd37df969959718
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c66d928f2c9fa59e162c391fbdd37df969959718

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Jul 17 14:33:15 2014 -0700

i965: Enable INTDIV in SIMD16 mode.

All we need to do is decompose this to two SIMD8 instructions, like we
do in many other cases.  We even already have code for that.

I apparently just botched this last time I tried, and it was easy.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_fs.cpp           |   12 ------------
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |    4 ++--
 2 files changed, 2 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 8405502..35ada42 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1404,18 +1404,6 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
    int base_mrf = 2;
    fs_inst *inst;
 
-   switch (opcode) {
-   case SHADER_OPCODE_INT_QUOTIENT:
-   case SHADER_OPCODE_INT_REMAINDER:
-      if (brw->gen >= 7)
-	 no16("SIMD16 INTDIV unsupported\n");
-      break;
-   case SHADER_OPCODE_POW:
-      break;
-   default:
-      unreachable("not reached: unsupported binary math opcode.");
-   }
-
    if (brw->gen >= 8) {
       inst = emit(opcode, dst, src0, src1);
    } else if (brw->gen >= 6) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 9e260a7..1190f1f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1620,9 +1620,9 @@ fs_generator::generate_code(exec_list *instructions)
       case SHADER_OPCODE_INT_REMAINDER:
       case SHADER_OPCODE_POW:
          assert(brw->gen < 6 || inst->mlen == 0);
-	 if (brw->gen >= 7) {
+	 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
             gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
-	 } else if (brw->gen == 6) {
+	 } else if (brw->gen >= 6) {
 	    generate_math_gen6(inst, dst, src[0], src[1]);
 	 } else {
 	    generate_math_gen4(inst, dst, src[0]);