Mesa (master): r600g: clear constant buffer sizes at the beginning of CS
Marek Olšák
mareko at kemper.freedesktop.org
Thu Aug 14 18:46:07 UTC 2014
Module: Mesa
Branch: master
Commit: d52202141ebe28cd9f8d305827552fafccb279fd
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d52202141ebe28cd9f8d305827552fafccb279fd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 31 02:33:12 2014 +0200
r600g: clear constant buffer sizes at the beginning of CS
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
---
src/gallium/drivers/r600/evergreen_state.c | 104 ++++++++++------------------
src/gallium/drivers/r600/evergreend.h | 1 +
src/gallium/drivers/r600/r600_state.c | 31 ++++-----
3 files changed, 49 insertions(+), 87 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index c141f6b..602c187 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2182,9 +2182,9 @@ void cayman_init_common_regs(struct r600_command_buffer *cb,
static void cayman_init_atom_start_cs(struct r600_context *rctx)
{
struct r600_command_buffer *cb = &rctx->start_cs_cmd;
- int tmp;
+ int tmp, i;
- r600_init_command_buffer(cb, 256);
+ r600_init_command_buffer(cb, 320);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -2297,40 +2297,24 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
/* to avoid GPU doing any preloading of constant from random address */
r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
- r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
- r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
if (rctx->screen->b.has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
@@ -2474,14 +2458,14 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
int num_hs_stack_entries;
int num_ls_stack_entries;
enum radeon_family family;
- unsigned tmp;
+ unsigned tmp, i;
if (rctx->b.chip_class == CAYMAN) {
cayman_init_atom_start_cs(rctx);
return;
}
- r600_init_command_buffer(cb, 256);
+ r600_init_command_buffer(cb, 320);
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -2754,40 +2738,24 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
/* to avoid GPU doing any preloading of constant from random address */
r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
- r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
- r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 8ea6aed..784d495 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1755,6 +1755,7 @@
#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180
#define R_028184_ALU_CONST_BUFFER_SIZE_VS_1 0x00028184
#define R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0 0x000281C0
+#define R_028F80_ALU_CONST_BUFFER_SIZE_HS_0 0x00028F80
#define R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0 0x00028FC0
#define R_028200_PA_SC_WINDOW_OFFSET 0x00028200
#define R_02820C_PA_SC_CLIPRECT_RULE 0x0002820C
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 43c5e70..607b199 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2083,7 +2083,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
int num_es_stack_entries;
enum radeon_family family;
struct r600_command_buffer *cb = &rctx->start_cs_cmd;
- uint32_t tmp;
+ uint32_t tmp, i;
r600_init_command_buffer(cb, 256);
@@ -2293,24 +2293,17 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
/* to avoid GPU doing any preloading of constant from random address */
- r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
- r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
- r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
+ r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
+ for (i = 0; i < 16; i++)
+ r600_store_value(cb, 0);
r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
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