Mesa (master): i965/skl: Fix SBE state upload code.

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: c914247dcb7c44c25efc335413da2d9d83fe550f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c914247dcb7c44c25efc335413da2d9d83fe550f

Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Sat Nov 22 15:22:15 2014 -0800

i965/skl: Fix SBE state upload code.

The state upload code was incorrectly shifting the attribute swizzles. The
effect of this is we're likely to get the default swizzle values, which disables
the component.

This doesn't technically fix any bugs since Skylake support is still disabled by
default (no PCI IDs).

While here, since VARYING_SLOT_MAX can be greater than the number of attributes
we have available, add a warning to the code to make sure we never do the wrong
thing (and hopefully prevent further static analysis from finding this).
Admittedly I am a bit confused. It seems to me like the moment a user has
greater than 8 varyings we will hit this condition. CC Ken to clarify.

v2: Forgot to git add the warning message in v1

v3: Change the > 31 varyings to an assertion (Ken)

Reported-by: Ilia Mirkin <imirkin at alum.mit.edu> (via Coverity)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/gen8_sf_state.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index f6cb3dd..0e514c6 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -93,10 +93,12 @@ upload_sbe(struct brw_context *brw)
          if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
             continue;
 
+         assert(input_index < 32);
+
          if (input_index < 16)
             dw4 |= (GEN9_SBE_ACTIVE_COMPONENT_XYZW << (input_index << 1));
          else
-            dw5 |= (GEN9_SBE_ACTIVE_COMPONENT_XYZW << (input_index << 1));
+            dw5 |= (GEN9_SBE_ACTIVE_COMPONENT_XYZW << ((input_index - 16) << 1));
 
          ++input_index;
       }