Mesa (broadwell): i965: Rework 3DSTATE_VS for Broadwell.
Kenneth Graunke
kwg at kemper.freedesktop.org
Sat Feb 1 01:12:10 UTC 2014
Module: Mesa
Branch: broadwell
Commit: 70bdd6bf0eb6cec708d2d47bd1a54506dc8bdd4b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=70bdd6bf0eb6cec708d2d47bd1a54506dc8bdd4b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:10:19 2012 -0800
i965: Rework 3DSTATE_VS for Broadwell.
v2: Remove incorrect MOCS shifts; rename urb_entry_write_offset to
urb_entry_output_offset to closer match the documentation.
v3: Only emit a non-zero constant buffer read length when active.
v4: Add missing binding table counts (caught by Eric).
v5: Rebase on Paul Berry's changes to CurrentVertexProgram.
v6: Drop bogus SBE read length/offset field code. We were programming
the wrong values, and our 3DSTATE_SBE code overrides any value we
put here anyway with the correct one.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v4]
---
src/mesa/drivers/dri/i965/Makefile.sources | 3 +-
src/mesa/drivers/dri/i965/brw_defines.h | 4 +
src/mesa/drivers/dri/i965/brw_state.h | 7 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
src/mesa/drivers/dri/i965/gen8_vs_state.c | 131 ++++++++++++++++++++++++++
5 files changed, 144 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index b0f84b9..57cc6b9 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -148,5 +148,6 @@ i965_FILES = \
gen8_instruction.c \
gen8_sf_state.c \
gen8_vec4_generator.cpp \
- gen8_wm_depth_stencil.cpp \
+ gen8_vs_state.c \
+ gen8_wm_depth_stencil.c \
$()
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 72f41ad..a3fe2dd 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1455,6 +1455,10 @@ enum brw_message_target {
# define GEN6_VS_STATISTICS_ENABLE (1 << 10)
# define GEN6_VS_CACHE_DISABLE (1 << 1)
# define GEN6_VS_ENABLE (1 << 0)
+/* Gen8+ DW8 */
+# define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21
+# define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT 16
+# define GEN8_VS_USER_CLIP_DISTANCE_SHIFT 8
#define _3DSTATE_GS 0x7811 /* GEN6+ */
/* DW2 */
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 669c163..2b72903 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -136,7 +136,7 @@ extern const struct brw_tracked_state gen8_wm_depth_stencil;
extern const struct brw_tracked_state gen8_raster_state;
extern const struct brw_tracked_state gen8_sbe_state;
extern const struct brw_tracked_state gen8_sf_state;
-
+extern const struct brw_tracked_state gen8_vs_state;
/* brw_misc_state.c */
void brw_upload_invariant_state(struct brw_context *brw);
@@ -253,6 +253,11 @@ gen7_upload_constant_state(struct brw_context *brw,
const struct brw_stage_state *stage_state,
bool active, unsigned opcode);
+/* gen8_vs_state.c */
+void
+gen8_upload_constant_state(struct brw_context *brw,
+ const struct brw_stage_state *stage_state,
+ bool active, unsigned opcode);
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index f913687..e78f590 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -297,7 +297,7 @@ static const struct brw_tracked_state *gen8_atoms[] =
&gen6_multisample_state,
&gen7_disable_stages,
- &gen7_vs_state,
+ &gen8_vs_state,
&gen7_gs_state,
&gen7_sol_state,
&gen7_clip_state,
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
new file mode 100644
index 0000000..65a62f3
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright © 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "program/prog_parameter.h"
+#include "program/prog_statevars.h"
+#include "intel_batchbuffer.h"
+
+void
+gen8_upload_constant_state(struct brw_context *brw,
+ const struct brw_stage_state *stage_state,
+ bool active, unsigned opcode)
+{
+ /* Disable if the shader stage is inactive or there are no push constants. */
+ active = active && stage_state->push_const_size != 0;
+
+ BEGIN_BATCH(11);
+ OUT_BATCH(opcode << 16 | (11 - 2));
+ OUT_BATCH(active ? stage_state->push_const_size : 0);
+ OUT_BATCH(0);
+ OUT_BATCH(active ? stage_state->push_const_offset : 0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
+
+static void
+upload_vs_state(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ const struct brw_stage_state *stage_state = &brw->vs.base;
+ uint32_t floating_point_mode = 0;
+
+ /* CACHE_NEW_VS_PROG */
+ const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
+
+ /* BRW_NEW_VS_BINDING_TABLE */
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
+ OUT_BATCH(stage_state->bind_bo_offset);
+ ADVANCE_BATCH();
+
+ /* CACHE_NEW_SAMPLER */
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
+ OUT_BATCH(stage_state->sampler_offset);
+ ADVANCE_BATCH();
+
+ gen8_upload_constant_state(brw, stage_state, true /* active */,
+ _3DSTATE_CONSTANT_VS);
+
+ /* Use ALT floating point mode for ARB vertex programs, because they
+ * require 0^0 == 1.
+ */
+ if (ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] == NULL)
+ floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
+
+ BEGIN_BATCH(9);
+ OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
+ OUT_BATCH(stage_state->prog_offset);
+ OUT_BATCH(0);
+ OUT_BATCH(GEN6_VS_VECTOR_MASK_ENABLE | floating_point_mode |
+ ((ALIGN(stage_state->sampler_count, 4) / 4) <<
+ GEN6_VS_SAMPLER_COUNT_SHIFT) |
+ ((prog_data->base.binding_table.size_bytes / 4) <<
+ GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+
+ if (prog_data->total_scratch) {
+ OUT_RELOC64(stage_state->scratch_bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ ffs(prog_data->total_scratch) - 11);
+ } else {
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ }
+
+ OUT_BATCH((prog_data->dispatch_grf_start_reg <<
+ GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+ (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
+ (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
+
+ OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
+ GEN6_VS_STATISTICS_ENABLE |
+ GEN6_VS_ENABLE);
+
+ /* _NEW_TRANSFORM */
+ OUT_BATCH((ctx->Transform.ClipPlanesEnabled <<
+ GEN8_VS_USER_CLIP_DISTANCE_SHIFT));
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen8_vs_state = {
+ .dirty = {
+ .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
+ .brw = BRW_NEW_CONTEXT |
+ BRW_NEW_VERTEX_PROGRAM |
+ BRW_NEW_VS_BINDING_TABLE |
+ BRW_NEW_BATCH |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION,
+ .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
+ },
+ .emit = upload_vs_state,
+};
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