Mesa (broadwell): i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
Kenneth Graunke
kwg at kemper.freedesktop.org
Sat Feb 1 01:12:10 UTC 2014
Module: Mesa
Branch: broadwell
Commit: a91d9f121fa309613d4b88e6c2c1115608b452ad
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a91d9f121fa309613d4b88e6c2c1115608b452ad
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
v2: Fix setting of GEN8_PSX_ATTRIBUTE_ENABLE after rebases.
v3: Add missing binding table entry counts. Don't worry about alpha
testing or alpha to coverage when setting the "Kill Pixel" bit;
those are specified in 3DSTATE_PS_BLEND (caught by Eric Anholt).
Drop unused _NEW_BUFFERS. Tidy comments.
v4: Rebase on Paul Berry's changes to CurrentFragmentProgram.
v5: Re-enable line stippling. It doesn't crash or anything.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v3]
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_defines.h | 20 +++
src/mesa/drivers/dri/i965/brw_state.h | 3 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 5 +-
src/mesa/drivers/dri/i965/gen8_ps_state.c | 210 ++++++++++++++++++++++++++
5 files changed, 237 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 57cc6b9..7092cc9 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -150,4 +150,5 @@ i965_FILES = \
gen8_vec4_generator.cpp \
gen8_vs_state.c \
gen8_wm_depth_stencil.c \
+ gen8_ps_state.c \
$()
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index a3fe2dd..a7f5d1a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1719,6 +1719,26 @@ enum brw_message_target {
# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT 0
+#define _3DSTATE_PS_EXTRA 0x784F /* GEN8+ */
+/* DW1 */
+# define GEN8_PSX_PIXEL_SHADER_VALID (1 << 31)
+# define GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE (1 << 30)
+# define GEN8_PSX_OMASK_TO_RENDER_TARGET (1 << 29)
+# define GEN8_PSX_KILL_ENABLE (1 << 28)
+# define GEN8_PSX_PSCDEPTH_OFF (0 << 26)
+# define GEN8_PSX_PSCDEPTH_ON (1 << 26)
+# define GEN8_PSX_PSCDEPTH_ON_GE (2 << 26)
+# define GEN8_PSX_PSCDEPTH_ON_LE (3 << 26)
+# define GEN8_PSX_FORCE_COMPUTED_DEPTH (1 << 25)
+# define GEN8_PSX_USES_SOURCE_DEPTH (1 << 24)
+# define GEN8_PSX_USES_SOURCE_W (1 << 23)
+# define GEN8_PSX_ATTRIBUTE_ENABLE (1 << 8)
+# define GEN8_PSX_SHADER_DISABLES_ALPHA_TO_COVERAGE (1 << 7)
+# define GEN8_PSX_SHADER_IS_PER_SAMPLE (1 << 6)
+# define GEN8_PSX_SHADER_COMPUTES_STENCIL (1 << 5)
+# define GEN8_PSX_SHADER_HAS_UAV (1 << 2)
+# define GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK (1 << 1)
+
enum brw_wm_barycentric_interp_mode {
BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC = 0,
BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC = 1,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 2b72903..3947904 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -132,7 +132,10 @@ extern const struct brw_tracked_state gen7_vs_state;
extern const struct brw_tracked_state gen7_wm_state;
extern const struct brw_tracked_state haswell_cut_index;
extern const struct brw_tracked_state gen8_ps_blend;
+extern const struct brw_tracked_state gen8_ps_extra;
+extern const struct brw_tracked_state gen8_ps_state;
extern const struct brw_tracked_state gen8_wm_depth_stencil;
+extern const struct brw_tracked_state gen8_wm_state;
extern const struct brw_tracked_state gen8_raster_state;
extern const struct brw_tracked_state gen8_sbe_state;
extern const struct brw_tracked_state gen8_sf_state;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index e78f590..86741a6 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -305,9 +305,10 @@ static const struct brw_tracked_state *gen8_atoms[] =
&gen8_sbe_state,
&gen8_sf_state,
&gen8_ps_blend,
+ &gen8_ps_extra,
+ &gen8_ps_state,
&gen8_wm_depth_stencil,
- &gen7_wm_state,
- &gen7_ps_state,
+ &gen8_wm_state,
&gen6_scissor_state,
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
new file mode 100644
index 0000000..ab83e41
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <stdbool.h>
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_ps_extra(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw->fragment_program);
+ uint32_t dw1 = 0;
+
+ dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
+
+ if (fp->program.UsesKill)
+ dw1 |= GEN8_PSX_KILL_ENABLE;
+
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ if (brw->wm.prog_data->num_varying_inputs != 0)
+ dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
+
+ if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+ switch (fp->program.FragDepthLayout) {
+ case FRAG_DEPTH_LAYOUT_NONE:
+ case FRAG_DEPTH_LAYOUT_ANY:
+ dw1 |= GEN8_PSX_PSCDEPTH_ON;
+ break;
+ case FRAG_DEPTH_LAYOUT_GREATER:
+ dw1 |= GEN8_PSX_PSCDEPTH_ON_GE;
+ break;
+ case FRAG_DEPTH_LAYOUT_LESS:
+ dw1 |= GEN8_PSX_PSCDEPTH_ON_LE;
+ break;
+ case FRAG_DEPTH_LAYOUT_UNCHANGED:
+ break;
+ }
+ }
+
+ if (fp->program.Base.InputsRead & VARYING_BIT_POS)
+ dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
+
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
+ OUT_BATCH(dw1);
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen8_ps_extra = {
+ .dirty = {
+ .mesa = 0,
+ .brw = BRW_NEW_CONTEXT | BRW_NEW_FRAGMENT_PROGRAM,
+ .cache = 0,
+ },
+ .emit = upload_ps_extra,
+};
+
+static void
+upload_wm_state(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ uint32_t dw1 = 0;
+
+ dw1 |= GEN7_WM_STATISTICS_ENABLE;
+ dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
+ dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
+ dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
+
+ /* _NEW_LINE */
+ if (ctx->Line.StippleFlag)
+ dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
+
+ /* _NEW_POLYGON */
+ if (ctx->Polygon.StippleFlag)
+ dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
+
+ /* CACHE_NEW_WM_PROG */
+ dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
+ GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
+
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
+ OUT_BATCH(dw1);
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen8_wm_state = {
+ .dirty = {
+ .mesa = _NEW_LINE | _NEW_POLYGON,
+ .brw = BRW_NEW_CONTEXT,
+ .cache = CACHE_NEW_WM_PROG,
+ },
+ .emit = upload_wm_state,
+};
+
+static void
+upload_ps_state(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ uint32_t dw3 = 0, dw6 = 0, dw7 = 0;
+
+ /* BRW_NEW_PS_BINDING_TABLE */
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
+ OUT_BATCH(brw->wm.base.bind_bo_offset);
+ ADVANCE_BATCH();
+
+ /* CACHE_NEW_SAMPLER */
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
+ OUT_BATCH(brw->wm.base.sampler_offset);
+ ADVANCE_BATCH();
+
+ /* CACHE_NEW_WM_PROG */
+ gen8_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
+
+ /* Initialize the execution mask with VMask. Otherwise, derivatives are
+ * incorrect for subspans where some of the pixels are unlit. We believe
+ * the bit just didn't take effect in previous generations.
+ */
+ dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
+
+ /* CACHE_NEW_SAMPLER */
+ dw3 |=
+ (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
+
+ /* CACHE_NEW_WM_PROG */
+ dw3 |=
+ ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
+ GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
+
+ /* Use ALT floating point mode for ARB fragment programs, because they
+ * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
+ * rendering, CurrentFragmentProgram is used for this check to
+ * differentiate between the GLSL and non-GLSL cases.
+ */
+ if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
+ dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
+
+ dw6 |= (brw->max_wm_threads - 2) << HSW_PS_MAX_THREADS_SHIFT;
+
+ /* CACHE_NEW_WM_PROG */
+ if (brw->wm.prog_data->nr_params > 0)
+ dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
+
+ dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
+ if (brw->wm.prog_data->prog_offset_16)
+ dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
+
+ dw7 |=
+ brw->wm.prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0 |
+ brw->wm.prog_data->first_curbe_grf_16<< GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
+
+ BEGIN_BATCH(12);
+ OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
+ OUT_BATCH(brw->wm.base.prog_offset);
+ OUT_BATCH(0);
+ OUT_BATCH(dw3);
+ if (brw->wm.prog_data->total_scratch) {
+ OUT_RELOC64(brw->wm.base.scratch_bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ ffs(brw->wm.prog_data->total_scratch) - 11);
+ } else {
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ }
+ OUT_BATCH(dw6);
+ OUT_BATCH(dw7);
+ OUT_BATCH(0); /* kernel 1 pointer */
+ OUT_BATCH(0);
+ OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen8_ps_state = {
+ .dirty = {
+ .mesa = _NEW_PROGRAM_CONSTANTS,
+ .brw = BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_PS_BINDING_TABLE |
+ BRW_NEW_BATCH |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION,
+ .cache = CACHE_NEW_SAMPLER | CACHE_NEW_WM_PROG
+ },
+ .emit = upload_ps_state,
+};
More information about the mesa-commit
mailing list