Mesa (master): i965/gs: Fix EndPrimitive on Broadwell.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 4dd1002518505f65e112dc9be1a68593724a86f2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4dd1002518505f65e112dc9be1a68593724a86f2

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Jan 29 16:31:31 2014 -0800

i965/gs: Fix EndPrimitive on Broadwell.

My earlier patch (i965: Reserve space for "Vertex Count" in GS outputs.)
incremented Global Offset for most URB writes to make room for the new
"Vertex Count" field, but failed to shift the URB writes used for
writing control bits.

Confusingly, Global Offset must be incremented by 2 here, rather than 1.
The URB writes we use for actual data are HWord writes, which treat
Global Offset as a 256-bit offset.  These are OWord writes, so it's
treated as a 128-bit offset instead.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 40743cc..d57c619 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -409,6 +409,13 @@ vec4_gs_visitor::emit_control_data_bits()
       inst->force_writemask_all = true;
       inst = emit(GS_OPCODE_URB_WRITE);
       inst->urb_write_flags = urb_write_flags;
+      /* We need to increment Global Offset by 256-bits to make room for
+       * Broadwell's extra "Vertex Count" payload at the beginning of the
+       * URB entry.  Since this is an OWord message, Global Offset is counted
+       * in 128-bit units, so we must set it to 2.
+       */
+      if (brw->gen >= 8)
+         inst->offset = 2;
       inst->base_mrf = base_mrf;
       inst->mlen = 2;
    }