Mesa (master): i965/vec4: Fix off-by-one register class overallocation.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: af25addcd0aaf373bd91c6a0b6c97d4c73092f91
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=af25addcd0aaf373bd91c6a0b6c97d4c73092f91

Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 22 19:21:13 2013 -0800

i965/vec4: Fix off-by-one register class overallocation.

Reviewed-by: Paul Berry <stereotype441 at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 4ecc4a2..e7aab9d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -121,7 +121,7 @@ brw_vec4_alloc_reg_set(struct brw_context *brw)
    if (brw->gen >= 6)
       ra_set_allocate_round_robin(brw->vec4.regs);
    ralloc_free(brw->vec4.classes);
-   brw->vec4.classes = ralloc_array(brw, int, class_count + 1);
+   brw->vec4.classes = ralloc_array(brw, int, class_count);
 
    /* Now, add the registers to their classes, and add the conflicts
     * between them and the base GRF registers (and also each other).