Mesa (master): i965: Convert VUE map generation checks to if rather than switch.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 80c1b9349c861cc023c4f25c329a3c0ed4695b9e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=80c1b9349c861cc023c4f25c329a3c0ed4695b9e

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Feb 25 12:21:41 2014 -0800

i965: Convert VUE map generation checks to if rather than switch.

There are currently only two VUE map layouts: one for Gen4-5, and one
for everything else.  We keep having to add new "case N+1" labels for
every new hardware generation, and so far it's always been the same.

This patch makes it so we only have to do work in the case where
something actually changes.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/brw_vs.c |   13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 775901f..d3dbc8e 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -82,9 +82,7 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
    /* VUE header: format depends on chip generation and whether clipping is
     * enabled.
     */
-   switch (brw->gen) {
-   case 4:
-   case 5:
+   if (brw->gen < 6) {
       /* There are 8 dwords in VUE header pre-Ironlake:
        * dword 0-3 is indices, point width, clip flags.
        * dword 4-7 is ndc position
@@ -96,10 +94,7 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
       assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
       assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
       assign_vue_slot(vue_map, VARYING_SLOT_POS);
-      break;
-   case 6:
-   case 7:
-   case 8:
+   } else {
       /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
        * dword 0-3 of the header is indices, point width, clip flags.
        * dword 4-7 is the 4D space position
@@ -126,10 +121,6 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
          assign_vue_slot(vue_map, VARYING_SLOT_COL1);
       if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC1))
          assign_vue_slot(vue_map, VARYING_SLOT_BFC1);
-      break;
-   default:
-      assert (!"VUE map not known for this chip generation");
-      break;
    }
 
    /* The hardware doesn't care about the rest of the vertex outputs, so just