Mesa (master): radeonsi: disable HTILE for 1D-tiled depth-stencil buffers
Marek Olšák
mareko at kemper.freedesktop.org
Mon Jan 6 17:44:43 UTC 2014
Module: Mesa
Branch: master
Commit: 2748b7da7e2a65bc46d12187b27585902a88f0aa
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2748b7da7e2a65bc46d12187b27585902a88f0aa
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Dec 27 19:14:55 2013 +0100
radeonsi: disable HTILE for 1D-tiled depth-stencil buffers
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
---
src/gallium/drivers/radeon/r600_texture.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index c7ef277..caf3743 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -466,6 +466,11 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = rscreen->tiling_info.num_channels;
+ /* HTILE doesn't work with 1D tiling (there's massive corruption
+ * in glxgears). */
+ if (rtex->surface.level[0].mode != RADEON_SURF_MODE_2D)
+ return 0;
+
switch (num_pipes) {
case 2:
cl_width = 32;
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