Mesa (master): i965: Move common fields into backend_instruction.
Matt Turner
mattst88 at kemper.freedesktop.org
Sun Jul 6 05:51:54 UTC 2014
Module: Mesa
Branch: master
Commit: ab74a42eef781b05bab2c67acbd37484f0e3aa2f
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab74a42eef781b05bab2c67acbd37484f0e3aa2f
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jun 29 17:32:14 2014 -0700
i965: Move common fields into backend_instruction.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.h | 12 ------------
src/mesa/drivers/dri/i965/brw_shader.h | 13 +++++++++++++
src/mesa/drivers/dri/i965/brw_vec4.h | 13 -------------
3 files changed, 13 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 4781079..da4d373 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -183,31 +183,19 @@ public:
fs_reg dst;
fs_reg *src;
- uint32_t texture_offset; /**< Texture offset bitfield */
- uint32_t offset; /* spill/unspill offset */
-
uint8_t sources; /**< Number of fs_reg sources. */
- uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
* mod and predication.
*/
uint8_t flag_subreg;
- uint8_t mlen; /**< SEND message length */
uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
- int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
- uint8_t sampler;
- uint8_t target; /**< MRT target. */
- bool saturate:1;
bool eot:1;
bool header_present:1;
bool shadow_compare:1;
bool force_uncompressed:1;
bool force_sechalf:1;
- bool force_writemask_all:1;
- bool no_dd_clear:1;
- bool no_dd_check:1;
};
/**
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index a5eed91..7205a85 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -111,6 +111,19 @@ public:
const void *ir;
const char *annotation;
/** @} */
+
+ uint32_t texture_offset; /**< Texture offset bitfield */
+ uint32_t offset; /**< spill/unspill offset */
+ uint8_t sampler;
+ uint8_t mlen; /**< SEND message length */
+ int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
+ uint8_t target; /**< MRT target. */
+ uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
+
+ bool force_writemask_all:1;
+ bool no_dd_clear:1;
+ bool no_dd_check:1;
+ bool saturate:1;
};
enum instruction_scheduler_mode {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 4b6e638..21df552 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -215,23 +215,10 @@ public:
dst_reg dst;
src_reg src[3];
- bool saturate;
- bool force_writemask_all;
- bool no_dd_clear, no_dd_check;
-
- int conditional_mod; /**< BRW_CONDITIONAL_* */
-
- int sampler;
- uint32_t texture_offset; /**< Texture Offset bitfield */
- int target; /**< MRT target. */
bool shadow_compare;
enum brw_urb_write_flags urb_write_flags;
bool header_present;
- int mlen; /**< SEND message length */
- int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
-
- uint32_t offset; /* spill/unspill offset */
bool is_send_from_grf();
bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
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