Mesa (master): r600g: Implement GL_ARB_texture_query_lod

[Andreas Boll]

Module: Mesa
Branch: master
Commit: a48b615006942f92243fd7783f5ef9cf396be1d0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a48b615006942f92243fd7783f5ef9cf396be1d0

Author: Glenn Kennard <glenn.kennard at gmail.com>
Date:   Wed Jul 23 10:48:17 2014 +0200

r600g: Implement GL_ARB_texture_query_lod

Requires Evergreen or later

v2 (Andreas): Update relnotes/10.3

Reviewed-by: Alex Deucher <alexander.deucher at amd.com> (v1)

---

 docs/GL3.txt                           |    2 +-
 docs/relnotes/10.3.html                |    4 ++--
 src/gallium/drivers/r600/r600_pipe.c   |    2 +-
 src/gallium/drivers/r600/r600_shader.c |   13 ++++++++++++-
 4 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index f9e33b4..e386b66 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -119,7 +119,7 @@ GL 4.0:
   GL_ARB_texture_buffer_object_rgb32                   DONE (i965, nvc0, r600, radeonsi, softpipe)
   GL_ARB_texture_cube_map_array                        DONE (i965, nv50, nvc0, r600, radeonsi, softpipe)
   GL_ARB_texture_gather                                DONE (i965, nv50, nvc0, radeonsi, r600)
-  GL_ARB_texture_query_lod                             DONE (i965, nv50, nvc0, radeonsi)
+  GL_ARB_texture_query_lod                             DONE (i965, nv50, nvc0, r600, radeonsi)
   GL_ARB_transform_feedback2                           DONE (i965, nv50, nvc0, r600, radeonsi)
   GL_ARB_transform_feedback3                           DONE (i965, nv50, nvc0, r600, radeonsi)
 
diff --git a/docs/relnotes/10.3.html b/docs/relnotes/10.3.html
index 9a74230..f023ca6 100644
--- a/docs/relnotes/10.3.html
+++ b/docs/relnotes/10.3.html
@@ -51,9 +51,9 @@ Note: some of the new features are only available with certain drivers.
 <li>GL_ARB_sample_shading on radeonsi</li>
 <li>GL_ARB_stencil_texturing on nv50, nvc0, r600, and radeonsi</li>
 <li>GL_ARB_texture_cube_map_array on radeonsi</li>
-<li>GL_ARB_texture_gather on radeonsi, r600</li>
+<li>GL_ARB_texture_gather on r600, radeonsi</li>
 <li>GL_ARB_texture_query_levels on nv50, nvc0, llvmpipe, r600, radeonsi, softpipe</li>
-<li>GL_ARB_texture_query_lod on radeonsi</li>
+<li>GL_ARB_texture_query_lod on r600, radeonsi</li>
 <li>GL_ARB_viewport_array on nvc0</li>
 <li>GL_ARB_seamless_cubemap_per_texture on i965, llvmpipe, nvc0, r600, radeonsi, softpipe</li>
 <li>GL_ARB_fragment_layer_viewport on nv50, nvc0, llvmpipe, r600</li>
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index f243159..39edbcf 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -304,6 +304,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_CUBE_MAP_ARRAY:
 	case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
+	case PIPE_CAP_TEXTURE_QUERY_LOD:
 		return family >= CHIP_CEDAR ? 1 : 0;
 
 	/* Unsupported features. */
@@ -314,7 +315,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 	case PIPE_CAP_USER_VERTEX_BUFFERS:
 	case PIPE_CAP_TEXTURE_GATHER_SM5:
-	case PIPE_CAP_TEXTURE_QUERY_LOD:
 	case PIPE_CAP_SAMPLE_SHADING:
 	case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 	case PIPE_CAP_DRAW_INDIRECT:
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 9f4c301..0d9cb26 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -5104,13 +5104,21 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
 		tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
 		tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+		tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
+	}
+	else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
+		tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
+		tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+		tex.dst_sel_z = 7;
+		tex.dst_sel_w = 7;
 	}
 	else {
 		tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
 		tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
 		tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
+		tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
 	}
-	tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
+
 
 	if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
 		tex.src_sel_x = 4;
@@ -6666,6 +6674,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TG4,   0, FETCH_OP_GATHER4, tgsi_unsupported},
+	{TGSI_OPCODE_LODQ,	0, FETCH_OP_GET_LOD, tgsi_unsupported},
 	{TGSI_OPCODE_LAST,	0, ALU_OP0_NOP, tgsi_unsupported},
 };
 
@@ -6860,6 +6869,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TG4,   0, FETCH_OP_GATHER4, tgsi_tex},
+	{TGSI_OPCODE_LODQ,	0, FETCH_OP_GET_LOD, tgsi_tex},
 	{TGSI_OPCODE_LAST,	0, ALU_OP0_NOP, tgsi_unsupported},
 };
 
@@ -7055,5 +7065,6 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TG4,   0, FETCH_OP_GATHER4, tgsi_tex},
+	{TGSI_OPCODE_LODQ,	0, FETCH_OP_GET_LOD, tgsi_tex},
 	{TGSI_OPCODE_LAST,	0, ALU_OP0_NOP, tgsi_unsupported},
 };