Mesa (master): i965/fs: Properly precolor payload registers on GEN5 in SIMD16
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Fri Oct 24 23:25:37 UTC 2014
Module: Mesa
Branch: master
Commit: ee65f2b50d5a411e05fb4e0dbe26766a47305b59
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee65f2b50d5a411e05fb4e0dbe26766a47305b59
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 13 19:41:17 2014 -0700
i965/fs: Properly precolor payload registers on GEN5 in SIMD16
For GEN6 SIMD16 mode, we have to 2-align all the registers, so we only have
the even-numbered ones. This means that we have to divide the register
number by 2 when we precolor. This wasn't a problem before because we were
setting up the interference between ra_node registers wrong. This will be
fixed in the next commit.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index be02dfe..34ee40f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -390,7 +390,16 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
* The alternative would be to have per-physical-register classes, which
* would just be silly.
*/
- ra_set_node_reg(g, first_payload_node + i, i);
+ if (brw->intelScreen->devinfo->gen <= 5 && dispatch_width == 16) {
+ /* We have to divide by 2 here because we only have even numbered
+ * registers. Some of the payload registers will be odd, but
+ * that's ok because their physical register numbers have already
+ * been assigned. The only thing this is used for is interference.
+ */
+ ra_set_node_reg(g, first_payload_node + i, i / 2);
+ } else {
+ ra_set_node_reg(g, first_payload_node + i, i);
+ }
}
}
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