Mesa (master): freedreno/a3xx: more texture array fixes

[Rob Clark]

Module: Mesa
Branch: master
Commit: 49b8fb937f76d49fb5d2ed0d2c99e947a389d686
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=49b8fb937f76d49fb5d2ed0d2c99e947a389d686

Author: Rob Clark <robclark at freedesktop.org>
Date:   Sat Sep 13 16:14:17 2014 -0400

freedreno/a3xx: more texture array fixes

Signed-off-by: Rob Clark <robclark at freedesktop.org>

---

 src/gallium/drivers/freedreno/a3xx/fd3_texture.c |    2 +-
 src/gallium/drivers/freedreno/freedreno_screen.c |    6 ++--
 src/gallium/drivers/freedreno/ir3/ir3_compiler.c |   33 +++++++++++-----------
 3 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
index 8a5140f..36a877d 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
@@ -179,7 +179,7 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	case PIPE_TEXTURE_1D_ARRAY:
 	case PIPE_TEXTURE_2D_ARRAY:
 		so->texconst3 =
-				A3XX_TEX_CONST_3_DEPTH(u_minify(prsc->array_size, lvl)) |
+				A3XX_TEX_CONST_3_DEPTH(prsc->array_size - 1) |
 				A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[0].size0) |
 				A3XX_TEX_CONST_3_LAYERSZ2(rsc->slices[0].size0);
 		break;
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 4970fd2..99e6e71 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -241,11 +241,13 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
 	/* Texturing. */
 	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
-	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 		return MAX_MIP_LEVELS;
+	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+		return 11;
+
 	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
-		return 0;  /* TODO: a3xx+ should support (required in gles3) */
+		return (screen->gpu_id >= 300) ? 256 : 0;
 
 	/* Render targets. */
 	case PIPE_CAP_MAX_RENDER_TARGETS:
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
index 5d96187..7c58d6f 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -1095,10 +1095,15 @@ get_tex_info(struct ir3_compile_context *ctx,
 		.flags = IR3_INSTR_S,
 	};
 	static const struct tex_info tex1da = {
-		.order = { 0, -1,  2, -1 },  /* coord.xz */
+		.order = { 0, -1,  1, -1 },  /* coord.xy */
 		.src_wrmask = TGSI_WRITEMASK_XYZ,
 		.flags = IR3_INSTR_A,
 	};
+	static const struct tex_info tex1dsa = {
+		.order = { 0, -1,  1,  2 },  /* coord.xyz */
+		.src_wrmask = TGSI_WRITEMASK_XYZW,
+		.flags = IR3_INSTR_S | IR3_INSTR_A,
+	};
 	static const struct tex_info tex2d = {
 		.order = { 0,  1, -1, -1 },  /* coord.xy */
 		.src_wrmask = TGSI_WRITEMASK_XY,
@@ -1114,6 +1119,11 @@ get_tex_info(struct ir3_compile_context *ctx,
 		.src_wrmask = TGSI_WRITEMASK_XYZ,
 		.flags = IR3_INSTR_A,
 	};
+	static const struct tex_info tex2dsa = {
+		.order = { 0,  1,  2,  3 },  /* coord.xyzw */
+		.src_wrmask = TGSI_WRITEMASK_XYZW,
+		.flags = IR3_INSTR_S | IR3_INSTR_A,
+	};
 	static const struct tex_info tex3d = {
 		.order = { 0,  1,  2, -1 },  /* coord.xyz */
 		.src_wrmask = TGSI_WRITEMASK_XYZ,
@@ -1130,15 +1140,10 @@ get_tex_info(struct ir3_compile_context *ctx,
 		.flags = IR3_INSTR_P,
 	};
 	static const struct tex_info txp1ds = {
-		.order = { 0, -1,  2,  3 },  /* coord.xzw */
+		.order = { 0, -1,  2,  3 },  /* coord.xyz */
 		.src_wrmask = TGSI_WRITEMASK_XYZW,
 		.flags = IR3_INSTR_P | IR3_INSTR_S,
 	};
-	static const struct tex_info txp1da = {
-		.order = { 0, -1,  2,  3 },  /* coord.xzw */
-		.src_wrmask = TGSI_WRITEMASK_XYZW,
-		.flags = IR3_INSTR_P | IR3_INSTR_A,
-	};
 	static const struct tex_info txp2d = {
 		.order = { 0,  1,  3, -1 },  /* coord.xyw */
 		.src_wrmask = TGSI_WRITEMASK_XYZ,
@@ -1149,11 +1154,6 @@ get_tex_info(struct ir3_compile_context *ctx,
 		.src_wrmask = TGSI_WRITEMASK_XYZW,
 		.flags = IR3_INSTR_P | IR3_INSTR_S,
 	};
-	static const struct tex_info txp2da = {
-		.order = { 0,  1,  2,  3 },  /* coord.xyzw */
-		.src_wrmask = TGSI_WRITEMASK_XYZW,
-		.flags = IR3_INSTR_P | IR3_INSTR_A,
-	};
 	static const struct tex_info txp3d = {
 		.order = { 0,  1,  2,  3 },  /* coord.xyzw */
 		.src_wrmask = TGSI_WRITEMASK_XYZW,
@@ -1173,6 +1173,8 @@ get_tex_info(struct ir3_compile_context *ctx,
 			return &tex1ds;
 		case TGSI_TEXTURE_1D_ARRAY:
 			return &tex1da;
+		case TGSI_TEXTURE_SHADOW1D_ARRAY:
+			return &tex1dsa;
 		case TGSI_TEXTURE_2D:
 		case TGSI_TEXTURE_RECT:
 			return &tex2d;
@@ -1181,6 +1183,8 @@ get_tex_info(struct ir3_compile_context *ctx,
 			return &tex2ds;
 		case TGSI_TEXTURE_2D_ARRAY:
 			return &tex2da;
+		case TGSI_TEXTURE_SHADOW2D_ARRAY:
+			return &tex2dsa;
 		case TGSI_TEXTURE_3D:
 		case TGSI_TEXTURE_CUBE:
 			return &tex3d;
@@ -1198,16 +1202,12 @@ get_tex_info(struct ir3_compile_context *ctx,
 			return &txp1d;
 		case TGSI_TEXTURE_SHADOW1D:
 			return &txp1ds;
-		case TGSI_TEXTURE_1D_ARRAY:
-			return &txp1da;
 		case TGSI_TEXTURE_2D:
 		case TGSI_TEXTURE_RECT:
 			return &txp2d;
 		case TGSI_TEXTURE_SHADOW2D:
 		case TGSI_TEXTURE_SHADOWRECT:
 			return &txp2ds;
-		case TGSI_TEXTURE_2D_ARRAY:
-			return &txp2da;
 		case TGSI_TEXTURE_3D:
 		case TGSI_TEXTURE_CUBE:
 			return &txp3d;
@@ -1237,6 +1237,7 @@ static bool is_1d(unsigned tex)
 	case TGSI_TEXTURE_1D:
 	case TGSI_TEXTURE_SHADOW1D:
 	case TGSI_TEXTURE_1D_ARRAY:
+	case TGSI_TEXTURE_SHADOW1D_ARRAY:
 		return true;
 	default:
 		return false;