Mesa Release Notes

LLVM build-type	Mesa build-type
debug,checked	release,profile
Debug	`-DLLVM_USE_CRT_DEBUG=MTd`	`-DLLVM_USE_CRT_DEBUG=MT`
Release	`-DLLVM_USE_CRT_RELEASE=MTd`	`-DLLVM_USE_CRT_RELEASE=MT`

secs; + std::vector syms; + std::vector

secs; }; } diff --git a/src/gallium/state_trackers/clover/core/program.cpp b/src/gallium/state_trackers/clover/core/program.cpp index 50ac01b..0d6cc40 100644 --- a/src/gallium/state_trackers/clover/core/program.cpp +++ b/src/gallium/state_trackers/clover/core/program.cpp @@ -106,7 +106,7 @@ program::build_log(const device &dev) const { return _logs.count(&dev) ? _logs.find(&dev)->second : ""; } -const compat::vector & +const std::vector & program::symbols() const { if (_binaries.empty()) throw error(CL_INVALID_PROGRAM_EXECUTABLE); diff --git a/src/gallium/state_trackers/clover/core/program.hpp b/src/gallium/state_trackers/clover/core/program.hpp index 661fa03..183145e 100644 --- a/src/gallium/state_trackers/clover/core/program.hpp +++ b/src/gallium/state_trackers/clover/core/program.hpp @@ -60,7 +60,7 @@ namespace clover { std::string build_opts(const device &dev) const; std::string build_log(const device &dev) const; - const compat::vector &symbols() const; + const std::vector &symbols() const; unsigned kernel_ref_count() const; diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp b/src/gallium/state_trackers/clover/llvm/invocation.cpp index 2157909..7d2d941 100644 --- a/src/gallium/state_trackers/clover/llvm/invocation.cpp +++ b/src/gallium/state_trackers/clover/llvm/invocation.cpp @@ -340,11 +340,11 @@ namespace { PM.run(*mod); } - compat::vector + std::vector get_kernel_args(const llvm::Module *mod, const std::string &kernel_name, const clang::LangAS::Map &address_spaces) { - compat::vector args; + std::vector args; llvm::Function *kernel_func = mod->getFunction(kernel_name); llvm::DataLayout TD(mod); @@ -449,15 +449,16 @@ namespace { for (unsigned i = 0; i < kernels.size(); ++i) { std::string kernel_name = kernels[i]->getName(); - compat::vector args = + std::vector args = get_kernel_args(mod, kernel_name, address_spaces); m.syms.push_back(module::symbol(kernel_name, 0, i, args )); } header.num_bytes = llvm_bitcode.size(); - std::string data; - data.insert(0, (char*)(&header), sizeof(header)); + std::vector data; + data.insert(data.end(), (char*)(&header), + (char*)(&header) + sizeof(header)); data.insert(data.end(), llvm_bitcode.begin(), llvm_bitcode.end()); m.secs.push_back(module::section(0, module::section::text, @@ -622,15 +623,16 @@ namespace { // Store the generated ELF binary in the module's text section. header.num_bytes = code.size(); - std::string data; - data.append((char*)(&header), sizeof(header)); - data.append(code.begin(), code.end()); + std::vector data; + data.insert(data.end(), (char*)(&header), + (char*)(&header) + sizeof(header)); + data.insert(data.end(), code.begin(), code.end()); m.secs.push_back(module::section(0, module::section::text, header.num_bytes, data)); for (std::map::iterator i = kernel_offsets.begin(), e = kernel_offsets.end(); i != e; ++i) { - compat::vector args = + std::vector args = get_kernel_args(mod, i->first, address_spaces); m.syms.push_back(module::symbol(i->first, 0, i->second, args )); } diff --git a/src/gallium/state_trackers/clover/tgsi/compiler.cpp b/src/gallium/state_trackers/clover/tgsi/compiler.cpp index 9e959f7..b70104e 100644 --- a/src/gallium/state_trackers/clover/tgsi/compiler.cpp +++ b/src/gallium/state_trackers/clover/tgsi/compiler.cpp @@ -40,7 +40,7 @@ namespace { std::istringstream ts(line); std::string name, tok; module::size_t offset; - compat::vector args; + std::vector args; if (!(ts >> name)) continue; @@ -83,7 +83,8 @@ namespace { throw build_error("translate failed"); unsigned sz = tgsi_num_tokens(prog) * sizeof(tgsi_token); - m.secs.push_back({ 0, module::section::text, sz, { (char *)prog, sz } }); + std::vector data( (char *)prog, (char *)prog + sz ); + m.secs.push_back({ 0, module::section::text, sz, data }); } } diff --git a/src/gallium/state_trackers/clover/util/compat.hpp b/src/gallium/state_trackers/clover/util/compat.hpp deleted file mode 100644 index dc06334..0000000 --- a/src/gallium/state_trackers/clover/util/compat.hpp +++ /dev/null @@ -1,313 +0,0 @@ -// -// Copyright 2012 Francisco Jerez -// -// Permission is hereby granted, free of charge, to any person obtaining a -// copy of this software and associated documentation files (the "Software"), -// to deal in the Software without restriction, including without limitation -// the rights to use, copy, modify, merge, publish, distribute, sublicense, -// and/or sell copies of the Software, and to permit persons to whom the -// Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR -// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -// OTHER DEALINGS IN THE SOFTWARE. -// - -#ifndef CLOVER_UTIL_COMPAT_HPP -#define CLOVER_UTIL_COMPAT_HPP - -#include -#include -#include -#include -#include - -namespace clover { - namespace compat { - // XXX - For cases where we can't rely on STL... I.e. the - // interface between code compiled as C++98 and C++11 - // source. Get rid of this as soon as everything can be - // compiled as C++11. - - namespace detail { - template - bool - ranges_equal(const R &a, const S &b) { - if (a.size() != b.size()) - return false; - - for (size_t i = 0; i < a.size(); ++i) - if (a[i] != b[i]) - return false; - - return true; - } - } - - template - class vector { - protected: - static T * - alloc(int n, const T *q, int m) { - T *p = reinterpret_cast(std::malloc(n * sizeof(T))); - - for (int i = 0; i < m; ++i) - new(&p[i]) T(q[i]); - - return p; - } - - static void - free(int n, T *p) { - for (int i = 0; i < n; ++i) - p[i].~T(); - - std::free(p); - } - - public: - typedef T *iterator; - typedef const T *const_iterator; - typedef T value_type; - typedef T &reference; - typedef const T &const_reference; - typedef std::ptrdiff_t difference_type; - typedef std::size_t size_type; - - vector() : p(NULL), _size(0), _capacity(0) { - } - - vector(const vector &v) : - p(alloc(v._size, v.p, v._size)), - _size(v._size), _capacity(v._size) { - } - - vector(const_iterator p, size_type n) : - p(alloc(n, p, n)), _size(n), _capacity(n) { - } - - template - vector(const C &v) : - p(alloc(v.size(), NULL, 0)), _size(0), - _capacity(v.size()) { - for (typename C::const_iterator it = v.begin(); it != v.end(); ++it) - new(&p[_size++]) T(*it); - } - - ~vector() { - free(_size, p); - } - - vector & - operator=(const vector &v) { - free(_size, p); - - p = alloc(v._size, v.p, v._size); - _size = v._size; - _capacity = v._size; - - return *this; - } - - bool - operator==(const vector &v) const { - return detail::ranges_equal(*this, v); - } - - void - reserve(size_type n) { - if (_capacity < n) { - T *q = alloc(n, p, _size); - free(_size, p); - - p = q; - _capacity = n; - } - } - - void - resize(size_type n, T x = T()) { - if (n <= _size) { - for (size_type i = n; i < _size; ++i) - p[i].~T(); - - } else { - reserve(n); - - for (size_type i = _size; i < n; ++i) - new(&p[i]) T(x); - } - - _size = n; - } - - void - push_back(const T &x) { - reserve(_size + 1); - new(&p[_size]) T(x); - ++_size; - } - - size_type - size() const { - return _size; - } - - size_type - capacity() const { - return _capacity; - } - - iterator - begin() { - return p; - } - - const_iterator - begin() const { - return p; - } - - iterator - end() { - return p + _size; - } - - const_iterator - end() const { - return p + _size; - } - - reference - operator[](size_type i) { - return p[i]; - } - - const_reference - operator[](size_type i) const { - return p[i]; - } - - private: - iterator p; - size_type _size; - size_type _capacity; - }; - - template - class vector_ref { - public: - typedef T *iterator; - typedef const T *const_iterator; - typedef T value_type; - typedef T &reference; - typedef const T &const_reference; - typedef std::ptrdiff_t difference_type; - typedef std::size_t size_type; - - vector_ref(iterator p, size_type n) : p(p), n(n) { - } - - template - vector_ref(C &v) : p(&*v.begin()), n(v.size()) { - } - - bool - operator==(const vector_ref &v) const { - return detail::ranges_equal(*this, v); - } - - size_type - size() const { - return n; - } - - iterator - begin() { - return p; - } - - const_iterator - begin() const { - return p; - } - - iterator - end() { - return p + n; - } - - const_iterator - end() const { - return p + n; - } - - reference - operator[](int i) { - return p[i]; - } - - const_reference - operator[](int i) const { - return p[i]; - } - - private: - iterator p; - size_type n; - }; - - class istream { - public: - typedef vector_ref buffer_t; - - class error { - public: - virtual ~error() {} - }; - - istream(const buffer_t &buf) : buf(buf), offset(0) {} - - void - read(char *p, size_t n) { - if (offset + n > buf.size()) - throw error(); - - std::memcpy(p, buf.begin() + offset, n); - offset += n; - } - - private: - const buffer_t &buf; - size_t offset; - }; - - class ostream { - public: - typedef vector buffer_t; - - ostream(buffer_t &buf) : buf(buf), offset(buf.size()) {} - - void - write(const char *p, size_t n) { - buf.resize(offset + n); - std::memcpy(buf.begin() + offset, p, n); - offset += n; - } - - private: - buffer_t &buf; - size_t offset; - }; - - } -} - -#endif From mareko at kemper.freedesktop.org Wed Apr 29 20:05:24 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Wed, 29 Apr 2015 13:05:24 -0700 (PDT) Subject: Mesa (master): winsys/radeon: move radeon_winsys.h to drivers/radeon Message-ID: <20150429200524.1375B761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: dcfbc006b6b07d41338b87c64cdc01c36608087b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dcfbc006b6b07d41338b87c64cdc01c36608087b Author: Marek Ol??k Date: Thu Apr 16 22:50:33 2015 +0200 winsys/radeon: move radeon_winsys.h to drivers/radeon --- src/gallium/auxiliary/target-helpers/inline_drm_helper.h | 6 +++--- src/gallium/drivers/r300/r300_chipset.c | 2 +- src/gallium/drivers/r300/r300_context.h | 1 - src/gallium/drivers/r300/r300_screen.h | 2 +- src/gallium/drivers/radeon/Makefile.sources | 3 ++- src/gallium/drivers/radeon/r600_pipe_common.h | 2 +- src/gallium/drivers/radeon/radeon_uvd.c | 1 - src/gallium/drivers/radeon/radeon_uvd.h | 2 +- src/gallium/drivers/radeon/radeon_vce.c | 1 - src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 1 - src/gallium/drivers/radeon/radeon_video.c | 1 - src/gallium/drivers/radeon/radeon_video.h | 2 +- .../{winsys/radeon/drm => drivers/radeon}/radeon_winsys.h | 0 src/gallium/drivers/radeonsi/si_pm4.h | 2 +- src/gallium/targets/pipe-loader/pipe_r300.c | 2 +- src/gallium/targets/pipe-loader/pipe_r600.c | 2 +- src/gallium/targets/pipe-loader/pipe_radeonsi.c | 2 +- src/gallium/winsys/radeon/drm/Makefile.sources | 3 +-- src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 2 +- 19 files changed, 16 insertions(+), 21 deletions(-) diff --git a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h index 542ad43..d3c331d 100644 --- a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h +++ b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h @@ -28,19 +28,19 @@ #endif #if GALLIUM_R300 -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "radeon/drm/radeon_drm_public.h" #include "r300/r300_public.h" #endif #if GALLIUM_R600 -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "radeon/drm/radeon_drm_public.h" #include "r600/r600_public.h" #endif #if GALLIUM_RADEONSI -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "radeon/drm/radeon_drm_public.h" #include "radeonsi/si_public.h" #endif diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index 7a83611..c1c7ce3 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -22,7 +22,7 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "r300_chipset.h" -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "util/u_debug.h" #include "util/u_memory.h" diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 4d2b153..3873c9a 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -36,7 +36,6 @@ #include "r300_defines.h" #include "r300_screen.h" #include "compiler/radeon_regalloc.h" -#include "radeon/drm/radeon_winsys.h" struct u_upload_mgr; struct r300_context; diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index f0dd3c6..7bba39b 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -25,7 +25,7 @@ #define R300_SCREEN_H #include "r300_chipset.h" -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "pipe/p_screen.h" #include "util/u_slab.h" #include "os/os_thread.h" diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 469f6d1..c655fe5 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -15,7 +15,8 @@ C_SOURCES := \ radeon_vce.c \ radeon_vce.h \ radeon_video.c \ - radeon_video.h + radeon_video.h \ + radeon_winsys.h LLVM_C_FILES := \ radeon_elf_util.c \ diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index faa6e0d..f1c9503 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -34,7 +34,7 @@ #include -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "util/u_blitter.h" #include "util/u_double_list.h" diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 9668d7d..4d4b54b 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -45,7 +45,6 @@ #include "vl/vl_defines.h" #include "vl/vl_mpeg12_decoder.h" -#include "radeon/drm/radeon_winsys.h" #include "r600_pipe_common.h" #include "radeon_video.h" #include "radeon_uvd.h" diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h index 462b101..41a6fb4 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.h +++ b/src/gallium/drivers/radeon/radeon_uvd.h @@ -34,7 +34,7 @@ #ifndef RADEON_UVD_H #define RADEON_UVD_H -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "vl/vl_video_buffer.h" /* UVD uses PM4 packet type 0 and 2 */ diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c index 6d34bd3..5f710e6 100644 --- a/src/gallium/drivers/radeon/radeon_vce.c +++ b/src/gallium/drivers/radeon/radeon_vce.c @@ -40,7 +40,6 @@ #include "vl/vl_video_buffer.h" -#include "radeon/drm/radeon_winsys.h" #include "r600_pipe_common.h" #include "radeon_video.h" #include "radeon_vce.h" diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c index b176aa7..0902957 100644 --- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c +++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c @@ -40,7 +40,6 @@ #include "vl/vl_video_buffer.h" -#include "radeon/drm/radeon_winsys.h" #include "r600_pipe_common.h" #include "radeon_video.h" #include "radeon_vce.h" diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index 1420798..6ec10c1 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -39,7 +39,6 @@ #include "vl/vl_defines.h" #include "vl/vl_video_buffer.h" -#include "radeon/drm/radeon_winsys.h" #include "r600_pipe_common.h" #include "radeon_video.h" #include "radeon_vce.h" diff --git a/src/gallium/drivers/radeon/radeon_video.h b/src/gallium/drivers/radeon/radeon_video.h index 974ea4f..6d0ff28 100644 --- a/src/gallium/drivers/radeon/radeon_video.h +++ b/src/gallium/drivers/radeon/radeon_video.h @@ -34,7 +34,7 @@ #ifndef RADEON_VIDEO_H #define RADEON_VIDEO_H -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "vl/vl_video_buffer.h" #define RVID_ERR(fmt, args...) \ diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h similarity index 100% rename from src/gallium/winsys/radeon/drm/radeon_winsys.h rename to src/gallium/drivers/radeon/radeon_winsys.h diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h index bfb5562..d215882 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.h +++ b/src/gallium/drivers/radeonsi/si_pm4.h @@ -27,7 +27,7 @@ #ifndef SI_PM4_H #define SI_PM4_H -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #define SI_PM4_MAX_DW 256 #define SI_PM4_MAX_BO 32 diff --git a/src/gallium/targets/pipe-loader/pipe_r300.c b/src/gallium/targets/pipe-loader/pipe_r300.c index abcade4..368b8c2 100644 --- a/src/gallium/targets/pipe-loader/pipe_r300.c +++ b/src/gallium/targets/pipe-loader/pipe_r300.c @@ -1,7 +1,7 @@ #include "target-helpers/inline_debug_helper.h" #include "state_tracker/drm_driver.h" #include "radeon/drm/radeon_drm_public.h" -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "r300/r300_public.h" static struct pipe_screen * diff --git a/src/gallium/targets/pipe-loader/pipe_r600.c b/src/gallium/targets/pipe-loader/pipe_r600.c index eb53637..65b11c8 100644 --- a/src/gallium/targets/pipe-loader/pipe_r600.c +++ b/src/gallium/targets/pipe-loader/pipe_r600.c @@ -1,7 +1,7 @@ #include "state_tracker/drm_driver.h" #include "target-helpers/inline_debug_helper.h" #include "radeon/drm/radeon_drm_public.h" -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "r600/r600_public.h" static struct pipe_screen * diff --git a/src/gallium/targets/pipe-loader/pipe_radeonsi.c b/src/gallium/targets/pipe-loader/pipe_radeonsi.c index 1dcd781..5457b5b 100644 --- a/src/gallium/targets/pipe-loader/pipe_radeonsi.c +++ b/src/gallium/targets/pipe-loader/pipe_radeonsi.c @@ -1,7 +1,7 @@ #include "state_tracker/drm_driver.h" #include "target-helpers/inline_debug_helper.h" #include "radeon/drm/radeon_drm_public.h" -#include "radeon/drm/radeon_winsys.h" +#include "radeon/radeon_winsys.h" #include "radeonsi/si_public.h" static struct pipe_screen * diff --git a/src/gallium/winsys/radeon/drm/Makefile.sources b/src/gallium/winsys/radeon/drm/Makefile.sources index d30969e..87a04fa 100644 --- a/src/gallium/winsys/radeon/drm/Makefile.sources +++ b/src/gallium/winsys/radeon/drm/Makefile.sources @@ -6,8 +6,7 @@ C_SOURCES := \ radeon_drm_cs.h \ radeon_drm_public.h \ radeon_drm_winsys.c \ - radeon_drm_winsys.h \ - radeon_winsys.h + radeon_drm_winsys.h TOOLS_HDR := \ radeon_ctx.h diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h index 5711ffa..ea475c8 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h @@ -30,7 +30,7 @@ #ifndef RADEON_DRM_WINSYS_H #define RADEON_DRM_WINSYS_H -#include "radeon_winsys.h" +#include "gallium/drivers/radeon/radeon_winsys.h" #include "os/os_thread.h" #include From mareko at kemper.freedesktop.org Wed Apr 29 20:05:24 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Wed, 29 Apr 2015 13:05:24 -0700 (PDT) Subject: Mesa (master): winsys/radeon: add a private interface for radeon_surface Message-ID: <20150429200524.1EC37761EA@kemper.freedesktop.org> Module: Mesa Branch: master Commit: a582b22c6382f24d921e9fe8a24917100c1396f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a582b22c6382f24d921e9fe8a24917100c1396f1 Author: Marek Ol??k Date: Thu Apr 16 22:53:04 2015 +0200 winsys/radeon: add a private interface for radeon_surface --- src/gallium/drivers/r600/evergreen_state.c | 6 +- src/gallium/drivers/r600/r600_uvd.c | 2 +- src/gallium/drivers/radeon/r600_pipe_common.h | 2 +- src/gallium/drivers/radeon/r600_texture.c | 12 +- src/gallium/drivers/radeon/radeon_uvd.c | 6 +- src/gallium/drivers/radeon/radeon_uvd.h | 4 +- src/gallium/drivers/radeon/radeon_vce.c | 2 +- src/gallium/drivers/radeon/radeon_vce.h | 6 +- src/gallium/drivers/radeon/radeon_video.c | 2 +- src/gallium/drivers/radeon/radeon_video.h | 2 +- src/gallium/drivers/radeon/radeon_winsys.h | 79 ++++++++- src/gallium/drivers/radeonsi/si_state.c | 4 +- src/gallium/drivers/radeonsi/si_uvd.c | 4 +- src/gallium/winsys/radeon/drm/Makefile.sources | 1 + src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 180 ++++++++++++++++++++ src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 20 +-- src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 1 + 17 files changed, 286 insertions(+), 47 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 266e372..4ddbc0b 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -664,7 +664,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, unsigned height, depth, width; unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; enum pipe_format pipe_format = state->format; - struct radeon_surface_level *surflevel; + struct radeon_surf_level *surflevel; unsigned base_level, first_level, last_level; uint64_t va; @@ -918,7 +918,7 @@ static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_ /** * This function intializes the CB* register values for RATs. It is meant * to be used for 1D aligned buffers that do not have an associated - * radeon_surface. + * radeon_surf. */ void evergreen_init_color_surface_rat(struct r600_context *rctx, struct r600_surface *surf) @@ -1163,7 +1163,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, struct r600_screen *rscreen = rctx->screen; struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; unsigned level = surf->base.u.tex.level; - struct radeon_surface_level *levelinfo = &rtex->surface.level[level]; + struct radeon_surf_level *levelinfo = &rtex->surface.level[level]; uint64_t offset; unsigned format, array_mode; unsigned macro_aspect, tile_split, bankh, bankw, nbanks; diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c index ee5288f..357e901 100644 --- a/src/gallium/drivers/r600/r600_uvd.c +++ b/src/gallium/drivers/r600/r600_uvd.c @@ -57,7 +57,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, { struct r600_context *ctx = (struct r600_context *)pipe; struct r600_texture *resources[VL_NUM_COMPONENTS] = {}; - struct radeon_surface* surfaces[VL_NUM_COMPONENTS] = {}; + struct radeon_surf* surfaces[VL_NUM_COMPONENTS] = {}; struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {}; const enum pipe_format *resource_formats; struct pipe_video_buffer template; diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index f1c9503..8d885ab 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -199,7 +199,7 @@ struct r600_texture { unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */ struct r600_texture *flushed_depth_texture; boolean is_flushing_texture; - struct radeon_surface surface; + struct radeon_surf surface; /* Colorbuffer compression and fast clear. */ struct r600_fmask_info fmask; diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index ab8ce7b..dc510c9 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -119,7 +119,7 @@ static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned leve } static int r600_init_surface(struct r600_common_screen *rscreen, - struct radeon_surface *surface, + struct radeon_surf *surface, const struct pipe_resource *ptex, unsigned array_mode, bool is_flushed_depth) @@ -234,7 +234,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, { struct r600_texture *rtex = (struct r600_texture*)ptex; struct r600_resource *resource = &rtex->resource; - struct radeon_surface *surface = &rtex->surface; + struct radeon_surf *surface = &rtex->surface; struct r600_common_screen *rscreen = (struct r600_common_screen*)screen; rscreen->ws->buffer_set_tiling(resource->buf, @@ -280,7 +280,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen, struct r600_fmask_info *out) { /* FMASK is allocated like an ordinary texture. */ - struct radeon_surface fmask = rtex->surface; + struct radeon_surf fmask = rtex->surface; memset(out, 0, sizeof(*out)); @@ -570,7 +570,7 @@ r600_texture_create_object(struct pipe_screen *screen, const struct pipe_resource *base, unsigned pitch_in_bytes_override, struct pb_buffer *buf, - struct radeon_surface *surface) + struct radeon_surf *surface) { struct r600_texture *rtex; struct r600_resource *resource; @@ -764,7 +764,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen, const struct pipe_resource *templ) { struct r600_common_screen *rscreen = (struct r600_common_screen*)screen; - struct radeon_surface surface = {0}; + struct radeon_surf surface = {0}; int r; r = r600_init_surface(rscreen, &surface, templ, @@ -790,7 +790,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen unsigned stride = 0; unsigned array_mode; enum radeon_bo_layout micro, macro; - struct radeon_surface surface; + struct radeon_surf surface; bool scanout; int r; diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 4d4b54b..be58d0b 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -870,7 +870,7 @@ error: } /* calculate top/bottom offset */ -static unsigned texture_offset(struct radeon_surface *surface, unsigned layer) +static unsigned texture_offset(struct radeon_surf *surface, unsigned layer) { return surface->level[0].offset + layer * surface->level[0].slice_size; @@ -905,8 +905,8 @@ static unsigned bank_wh(unsigned bankwh) /** * fill decoding target field from the luma and chroma surfaces */ -void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma, - struct radeon_surface *chroma) +void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma, + struct radeon_surf *chroma) { msg->body.decode.dt_pitch = luma->level[0].pitch_bytes; switch (luma->level[0].mode) { diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h index 41a6fb4..7442865 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.h +++ b/src/gallium/drivers/radeon/radeon_uvd.h @@ -353,6 +353,6 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context, ruvd_set_dtb set_dtb); /* fill decoding target field from the luma and chroma surfaces */ -void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma, - struct radeon_surface *chroma); +void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma, + struct radeon_surf *chroma); #endif diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c index 5f710e6..e220f40 100644 --- a/src/gallium/drivers/radeon/radeon_vce.c +++ b/src/gallium/drivers/radeon/radeon_vce.c @@ -337,7 +337,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context, struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen; struct rvce_encoder *enc; struct pipe_video_buffer *tmp_buf, templat = {}; - struct radeon_surface *tmp_surf; + struct radeon_surf *tmp_surf; unsigned cpb_size; if (!rscreen->info.vce_fw_version) { diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h index 7f0cd1f..5c6317a 100644 --- a/src/gallium/drivers/radeon/radeon_vce.h +++ b/src/gallium/drivers/radeon/radeon_vce.h @@ -50,7 +50,7 @@ struct r600_common_screen; /* driver dependent callback */ typedef void (*rvce_get_buffer)(struct pipe_resource *resource, struct radeon_winsys_cs_handle **handle, - struct radeon_surface **surface); + struct radeon_surf **surface); /* Coded picture buffer slot */ struct rvce_cpb_slot { @@ -88,8 +88,8 @@ struct rvce_encoder { rvce_get_buffer get_buffer; struct radeon_winsys_cs_handle* handle; - struct radeon_surface* luma; - struct radeon_surface* chroma; + struct radeon_surf* luma; + struct radeon_surf* chroma; struct radeon_winsys_cs_handle* bs_handle; unsigned bs_size; diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index 6ec10c1..826e076 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -132,7 +132,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) */ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind, struct pb_buffer** buffers[VL_NUM_COMPONENTS], - struct radeon_surface *surfaces[VL_NUM_COMPONENTS]) + struct radeon_surf *surfaces[VL_NUM_COMPONENTS]) { unsigned best_tiling, best_wh, off; unsigned size, alignment; diff --git a/src/gallium/drivers/radeon/radeon_video.h b/src/gallium/drivers/radeon/radeon_video.h index 6d0ff28..c9ee67f 100644 --- a/src/gallium/drivers/radeon/radeon_video.h +++ b/src/gallium/drivers/radeon/radeon_video.h @@ -68,7 +68,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) sumup their sizes and replace the backend buffers with a single bo */ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind, struct pb_buffer** buffers[VL_NUM_COMPONENTS], - struct radeon_surface *surfaces[VL_NUM_COMPONENTS]); + struct radeon_surf *surfaces[VL_NUM_COMPONENTS]); /* returns supported codecs and other parameters */ int rvid_get_video_param(struct pipe_screen *screen, diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index ee0a904..3bfbb6d 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -41,7 +41,6 @@ */ #include "pipebuffer/pb_buffer.h" -#include "radeon_surface.h" #define RADEON_MAX_CMDBUF_DWORDS (16 * 1024) @@ -246,6 +245,80 @@ enum radeon_feature_id { RADEON_FID_R300_CMASK_ACCESS, }; +#define RADEON_SURF_MAX_LEVEL 32 + +#define RADEON_SURF_TYPE_MASK 0xFF +#define RADEON_SURF_TYPE_SHIFT 0 +#define RADEON_SURF_TYPE_1D 0 +#define RADEON_SURF_TYPE_2D 1 +#define RADEON_SURF_TYPE_3D 2 +#define RADEON_SURF_TYPE_CUBEMAP 3 +#define RADEON_SURF_TYPE_1D_ARRAY 4 +#define RADEON_SURF_TYPE_2D_ARRAY 5 +#define RADEON_SURF_MODE_MASK 0xFF +#define RADEON_SURF_MODE_SHIFT 8 +#define RADEON_SURF_MODE_LINEAR 0 +#define RADEON_SURF_MODE_LINEAR_ALIGNED 1 +#define RADEON_SURF_MODE_1D 2 +#define RADEON_SURF_MODE_2D 3 +#define RADEON_SURF_SCANOUT (1 << 16) +#define RADEON_SURF_ZBUFFER (1 << 17) +#define RADEON_SURF_SBUFFER (1 << 18) +#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) +#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) +#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) +#define RADEON_SURF_FMASK (1 << 21) + +#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) +#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) +#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT)) + +struct radeon_surf_level { + uint64_t offset; + uint64_t slice_size; + uint32_t npix_x; + uint32_t npix_y; + uint32_t npix_z; + uint32_t nblk_x; + uint32_t nblk_y; + uint32_t nblk_z; + uint32_t pitch_bytes; + uint32_t mode; +}; + +struct radeon_surf { + /* These are inputs to the calculator. */ + uint32_t npix_x; + uint32_t npix_y; + uint32_t npix_z; + uint32_t blk_w; + uint32_t blk_h; + uint32_t blk_d; + uint32_t array_size; + uint32_t last_level; + uint32_t bpe; + uint32_t nsamples; + uint32_t flags; + + /* These are return values. Some of them can be set by the caller, but + * they will be treated as hints (e.g. bankw, bankh) and might be + * changed by the calculator. + */ + uint64_t bo_size; + uint64_t bo_alignment; + /* This applies to EG and later. */ + uint32_t bankw; + uint32_t bankh; + uint32_t mtilea; + uint32_t tile_split; + uint32_t stencil_tile_split; + uint64_t stencil_offset; + struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL]; + struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL]; + uint32_t tiling_index[RADEON_SURF_MAX_LEVEL]; + uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL]; +}; + struct radeon_winsys { /** * The screen object this winsys was created for @@ -576,7 +649,7 @@ struct radeon_winsys { * \param surf Surface structure ptr */ int (*surface_init)(struct radeon_winsys *ws, - struct radeon_surface *surf); + struct radeon_surf *surf); /** * Find best values for a surface @@ -585,7 +658,7 @@ struct radeon_winsys { * \param surf Surface structure ptr */ int (*surface_best)(struct radeon_winsys *ws, - struct radeon_surface *surf); + struct radeon_surf *surf); uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index dc19d29..7f0fdd5 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1852,7 +1852,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_screen *sscreen = sctx->screen; struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; unsigned level = surf->base.u.tex.level; - struct radeon_surface_level *levelinfo = &rtex->surface.level[level]; + struct radeon_surf_level *levelinfo = &rtex->surface.level[level]; unsigned format, tile_mode_index, array_mode; unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; uint32_t z_info, s_info, db_depth_info; @@ -2258,7 +2258,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx unsigned char state_swizzle[4], swizzle[4]; unsigned height, depth, width; enum pipe_format pipe_format = state->format; - struct radeon_surface_level *surflevel; + struct radeon_surf_level *surflevel; int first_non_void; uint64_t va; diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c index 0ba3b12..2f10f9b 100644 --- a/src/gallium/drivers/radeonsi/si_uvd.c +++ b/src/gallium/drivers/radeonsi/si_uvd.c @@ -44,7 +44,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe, { struct si_context *ctx = (struct si_context *)pipe; struct r600_texture *resources[VL_NUM_COMPONENTS] = {}; - struct radeon_surface *surfaces[VL_NUM_COMPONENTS] = {}; + struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {}; struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {}; const enum pipe_format *resource_formats; struct pipe_video_buffer template; @@ -136,7 +136,7 @@ static struct radeon_winsys_cs_handle* si_uvd_set_dtb(struct ruvd_msg *msg, stru /* get the radeon resources for VCE */ static void si_vce_get_buffer(struct pipe_resource *resource, struct radeon_winsys_cs_handle **handle, - struct radeon_surface **surface) + struct radeon_surf **surface) { struct r600_texture *res = (struct r600_texture *)resource; diff --git a/src/gallium/winsys/radeon/drm/Makefile.sources b/src/gallium/winsys/radeon/drm/Makefile.sources index 87a04fa..a00c84d 100644 --- a/src/gallium/winsys/radeon/drm/Makefile.sources +++ b/src/gallium/winsys/radeon/drm/Makefile.sources @@ -5,6 +5,7 @@ C_SOURCES := \ radeon_drm_cs_dump.c \ radeon_drm_cs.h \ radeon_drm_public.h \ + radeon_drm_surface.c \ radeon_drm_winsys.c \ radeon_drm_winsys.h diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c new file mode 100644 index 0000000..29d3467 --- /dev/null +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -0,0 +1,180 @@ +/* + * Copyright ? 2014 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * Authors: + * Marek Ol??k + */ + +#include "radeon_drm_winsys.h" + +#include + +static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm, + const struct radeon_surf_level *level_ws) +{ + level_drm->offset = level_ws->offset; + level_drm->slice_size = level_ws->slice_size; + level_drm->npix_x = level_ws->npix_x; + level_drm->npix_y = level_ws->npix_y; + level_drm->npix_z = level_ws->npix_z; + level_drm->nblk_x = level_ws->nblk_x; + level_drm->nblk_y = level_ws->nblk_y; + level_drm->nblk_z = level_ws->nblk_z; + level_drm->pitch_bytes = level_ws->pitch_bytes; + level_drm->mode = level_ws->mode; +} + +static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws, + const struct radeon_surface_level *level_drm) +{ + level_ws->offset = level_drm->offset; + level_ws->slice_size = level_drm->slice_size; + level_ws->npix_x = level_drm->npix_x; + level_ws->npix_y = level_drm->npix_y; + level_ws->npix_z = level_drm->npix_z; + level_ws->nblk_x = level_drm->nblk_x; + level_ws->nblk_y = level_drm->nblk_y; + level_ws->nblk_z = level_drm->nblk_z; + level_ws->pitch_bytes = level_drm->pitch_bytes; + level_ws->mode = level_drm->mode; +} + +static void surf_winsys_to_drm(struct radeon_surface *surf_drm, + const struct radeon_surf *surf_ws) +{ + int i; + + memset(surf_drm, 0, sizeof(*surf_drm)); + + surf_drm->npix_x = surf_ws->npix_x; + surf_drm->npix_y = surf_ws->npix_y; + surf_drm->npix_z = surf_ws->npix_z; + surf_drm->blk_w = surf_ws->blk_w; + surf_drm->blk_h = surf_ws->blk_h; + surf_drm->blk_d = surf_ws->blk_d; + surf_drm->array_size = surf_ws->array_size; + surf_drm->last_level = surf_ws->last_level; + surf_drm->bpe = surf_ws->bpe; + surf_drm->nsamples = surf_ws->nsamples; + surf_drm->flags = surf_ws->flags; + + surf_drm->bo_size = surf_ws->bo_size; + surf_drm->bo_alignment = surf_ws->bo_alignment; + + surf_drm->bankw = surf_ws->bankw; + surf_drm->bankh = surf_ws->bankh; + surf_drm->mtilea = surf_ws->mtilea; + surf_drm->tile_split = surf_ws->tile_split; + surf_drm->stencil_tile_split = surf_ws->stencil_tile_split; + surf_drm->stencil_offset = surf_ws->stencil_offset; + + for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) { + surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]); + surf_level_winsys_to_drm(&surf_drm->stencil_level[i], + &surf_ws->stencil_level[i]); + + surf_drm->tiling_index[i] = surf_ws->tiling_index[i]; + surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i]; + } +} + +static void surf_drm_to_winsys(struct radeon_surf *surf_ws, + const struct radeon_surface *surf_drm) +{ + int i; + + memset(surf_ws, 0, sizeof(*surf_ws)); + + surf_ws->npix_x = surf_drm->npix_x; + surf_ws->npix_y = surf_drm->npix_y; + surf_ws->npix_z = surf_drm->npix_z; + surf_ws->blk_w = surf_drm->blk_w; + surf_ws->blk_h = surf_drm->blk_h; + surf_ws->blk_d = surf_drm->blk_d; + surf_ws->array_size = surf_drm->array_size; + surf_ws->last_level = surf_drm->last_level; + surf_ws->bpe = surf_drm->bpe; + surf_ws->nsamples = surf_drm->nsamples; + surf_ws->flags = surf_drm->flags; + + surf_ws->bo_size = surf_drm->bo_size; + surf_ws->bo_alignment = surf_drm->bo_alignment; + + surf_ws->bankw = surf_drm->bankw; + surf_ws->bankh = surf_drm->bankh; + surf_ws->mtilea = surf_drm->mtilea; + surf_ws->tile_split = surf_drm->tile_split; + surf_ws->stencil_tile_split = surf_drm->stencil_tile_split; + surf_ws->stencil_offset = surf_drm->stencil_offset; + + for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) { + surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]); + surf_level_drm_to_winsys(&surf_ws->stencil_level[i], + &surf_drm->stencil_level[i]); + + surf_ws->tiling_index[i] = surf_drm->tiling_index[i]; + surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i]; + } +} + +static int radeon_winsys_surface_init(struct radeon_winsys *rws, + struct radeon_surf *surf_ws) +{ + struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; + struct radeon_surface surf_drm; + int r; + + surf_winsys_to_drm(&surf_drm, surf_ws); + + r = radeon_surface_init(ws->surf_man, &surf_drm); + if (r) + return r; + + surf_drm_to_winsys(surf_ws, &surf_drm); + return 0; +} + +static int radeon_winsys_surface_best(struct radeon_winsys *rws, + struct radeon_surf *surf_ws) +{ + struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; + struct radeon_surface surf_drm; + int r; + + surf_winsys_to_drm(&surf_drm, surf_ws); + + r = radeon_surface_best(ws->surf_man, &surf_drm); + if (r) + return r; + + surf_drm_to_winsys(surf_ws, &surf_drm); + return 0; +} + +void radeon_surface_init_functions(struct radeon_drm_winsys *ws) +{ + ws->base.surface_init = radeon_winsys_surface_init; + ws->base.surface_best = radeon_winsys_surface_best; +} diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index a6f847f..ba8d143 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -44,6 +44,7 @@ #include #include #include +#include #ifndef RADEON_INFO_ACTIVE_CU_COUNT #define RADEON_INFO_ACTIVE_CU_COUNT 0x20 @@ -514,22 +515,6 @@ static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs, return FALSE; } -static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws, - struct radeon_surface *surf) -{ - struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; - - return radeon_surface_init(ws->surf_man, surf); -} - -static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws, - struct radeon_surface *surf) -{ - struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; - - return radeon_surface_best(ws->surf_man, surf); -} - static uint64_t radeon_query_value(struct radeon_winsys *rws, enum radeon_value_id value) { @@ -740,13 +725,12 @@ radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create) ws->base.destroy = radeon_winsys_destroy; ws->base.query_info = radeon_query_info; ws->base.cs_request_feature = radeon_cs_request_feature; - ws->base.surface_init = radeon_drm_winsys_surface_init; - ws->base.surface_best = radeon_drm_winsys_surface_best; ws->base.query_value = radeon_query_value; ws->base.read_registers = radeon_read_registers; radeon_bomgr_init_functions(ws); radeon_drm_cs_init_functions(ws); + radeon_surface_init_functions(ws); pipe_mutex_init(ws->hyperz_owner_mutex); pipe_mutex_init(ws->cmask_owner_mutex); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h index ea475c8..166b6b9 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h @@ -103,5 +103,6 @@ radeon_drm_winsys(struct radeon_winsys *base) } void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs); +void radeon_surface_init_functions(struct radeon_drm_winsys *ws); #endif From idr at kemper.freedesktop.org Wed Apr 29 20:19:13 2015 From: idr at kemper.freedesktop.org (Ian Romanick) Date: Wed, 29 Apr 2015 13:19:13 -0700 (PDT) Subject: Mesa (master): glx: Massive update of comments in struct extension_info Message-ID: <20150429201913.BB756761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 2c7e289d8b1d3c63ab55b64ab3961067fd5a1985 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c7e289d8b1d3c63ab55b64ab3961067fd5a1985 Author: Ian Romanick Date: Wed Apr 15 11:34:50 2015 -0700 glx: Massive update of comments in struct extension_info In response to another patch, Emil asked for some clarification how this stuff works. Rather than just reply to the e-mail, I decided to update the exlanation in the code. Signed-off-by: Ian Romanick Cc: Emil Velikov --- src/glx/glxextensions.c | 69 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/src/glx/glxextensions.c b/src/glx/glxextensions.c index a326f0d..cb8cd66 100644 --- a/src/glx/glxextensions.c +++ b/src/glx/glxextensions.c @@ -61,12 +61,73 @@ struct extension_info */ unsigned char version_major; unsigned char version_minor; + + /** + * The client (i.e., libGL) supports this extension. + * + * Except during bring up, all extensions should have this set to Y. There + * are a few cases of extensions that have partial (or speculative) + * support, but these are rare. There also shouldn't be any new ones + * added. + * + * Generally, extensions require server support and ::client_support to be + * enabled. If the display is capable of direct rendering, + * ::direct_support is also required. + * + * \sa ::client_only + */ unsigned char client_support; + + /** + * The direct-renderer (e.g., i965_dri.so) supports this extension. + * + * For cases where all of the infrastructure to support the extension is a + * required part of the loader/driver interface, this can default to Y. + * For most cases, extended functionality, usually in the form of DRI2 + * extensions, is necessary to support the extension. The loader will set + * the flag true if all the requirements are met. + * + * If the display is capable of direct rendering, ::direct_support is + * required for the extension to be enabled. + */ unsigned char direct_support; - unsigned char client_only; /** Is the extension client-side only? */ - unsigned char direct_only; /** Is the extension for direct - * contexts only? - */ + + /** + * The extension depends only on client support. + * + * This is for extensions like GLX_ARB_get_proc_address that are contained + * entirely in the client library. There is no dependency on the server or + * the direct-renderer. + * + * These extensions will be enabled if ::client_support is set. + * + * \note + * An extension \b cannot be both client-only and direct-only because being + * direct-only implies a dependency on the direct renderer. + * + * \sa ::client_support, ::direct_only + */ + unsigned char client_only; + + /** + * The extension only functions with direct-rendering contexts + * + * The extension has no GLX protocol, and, therefore, no explicit + * dependency on the server. The functionality is contained entirely in + * the client library and the direct renderer. A few of the swap-related + * extensions are intended to behave this way. + * + * These extensions will be enabled if both ::client_support and + * ::direct_support are set. + * + * \note + * An extension \b cannot be both client-only and direct-only because being + * client-only implies that all functionality is outside the + * direct-renderer. + * + * \sa ::direct_support, ::client_only + */ + unsigned char direct_only; }; /* *INDENT-OFF* */ From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965: Expose and refactor brw_update_renderbuffer_surfaces( ) Message-ID: <20150429215500.79300761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: c15e20d8f6f6d632ad55d444149c2a12d0dcc515 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c15e20d8f6f6d632ad55d444149c2a12d0dcc515 Author: Topi Pohjolainen Date: Thu Mar 19 11:09:54 2015 +0200 i965: Expose and refactor brw_update_renderbuffer_surfaces() Note that brw_update_renderbuffer_surfaces() already had a helper variable which was used in parallel to direct access of the current draw buffer of the context. Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 5 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 51 +++++++++++++--------- 2 files changed, 35 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index cfa67b6..83058b9 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -233,6 +233,11 @@ GLuint translate_tex_format(struct brw_context *brw, int brw_get_texture_swizzle(const struct gl_context *ctx, const struct gl_texture_object *t); +void brw_update_renderbuffer_surfaces(struct brw_context *brw, + const struct gl_framebuffer *fb, + uint32_t render_target_start, + uint32_t *surf_offset); + /* gen7_wm_surface_state.c */ uint32_t gen7_surface_tiling_mode(uint32_t tiling); uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout l); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index d451940..25fb543 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -731,40 +731,49 @@ brw_update_renderbuffer_surface(struct brw_context *brw, /** * Construct SURFACE_STATE objects for renderbuffers/draw buffers. */ -static void -brw_update_renderbuffer_surfaces(struct brw_context *brw) +void +brw_update_renderbuffer_surfaces(struct brw_context *brw, + const struct gl_framebuffer *fb, + uint32_t render_target_start, + uint32_t *surf_offset) { - struct gl_context *ctx = &brw->ctx; - /* _NEW_BUFFERS */ - const struct gl_framebuffer *fb = ctx->DrawBuffer; GLuint i; - /* _NEW_BUFFERS | _NEW_COLOR */ /* Update surfaces for drawing buffers */ - if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { - const uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + i; + if (fb->_NumColorDrawBuffers >= 1) { + for (i = 0; i < fb->_NumColorDrawBuffers; i++) { + const uint32_t surf_index = render_target_start + i; - if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { - brw->wm.base.surf_offset[surf_index] = + if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) { + surf_offset[surf_index] = brw->vtbl.update_renderbuffer_surface( - brw, ctx->DrawBuffer->_ColorDrawBuffers[i], - ctx->DrawBuffer->MaxNumLayers > 0, i, surf_index); + brw, fb->_ColorDrawBuffers[i], + fb->MaxNumLayers > 0, i, surf_index); } else { brw->vtbl.emit_null_surface_state( brw, fb->Width, fb->Height, fb->Visual.samples, - &brw->wm.base.surf_offset[surf_index]); + &surf_offset[surf_index]); } } } else { - const uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start; - + const uint32_t surf_index = render_target_start; brw->vtbl.emit_null_surface_state( brw, fb->Width, fb->Height, fb->Visual.samples, - &brw->wm.base.surf_offset[surf_index]); + &surf_offset[surf_index]); } +} + +static void +update_renderbuffer_surfaces(struct brw_context *brw) +{ + const struct gl_context *ctx = &brw->ctx; + + /* _NEW_BUFFERS | _NEW_COLOR */ + const struct gl_framebuffer *fb = ctx->DrawBuffer; + brw_update_renderbuffer_surfaces( + brw, fb, + brw->wm.prog_data->binding_table.render_target_start, + brw->wm.base.surf_offset); brw->ctx.NewDriverState |= BRW_NEW_SURFACES; } @@ -775,7 +784,7 @@ const struct brw_tracked_state brw_renderbuffer_surfaces = { .brw = BRW_NEW_BATCH | BRW_NEW_FS_PROG_DATA, }, - .emit = brw_update_renderbuffer_surfaces, + .emit = update_renderbuffer_surfaces, }; const struct brw_tracked_state gen6_renderbuffer_surfaces = { @@ -783,7 +792,7 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces = { .mesa = _NEW_BUFFERS, .brw = BRW_NEW_BATCH, }, - .emit = brw_update_renderbuffer_surfaces, + .emit = update_renderbuffer_surfaces, }; From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965: Refactor sampler state setup Message-ID: <20150429215500.9C33A761EA@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 02dbc79297203a063b91e6b5a0b81bda8aa48c19 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=02dbc79297203a063b91e6b5a0b81bda8aa48c19 Author: Topi Pohjolainen Date: Thu Apr 2 12:45:02 2015 +0300 i965: Refactor sampler state setup v2 (Matt): Moved * to the name. Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_sampler_state.c | 60 ++++++++++++++++--------- src/mesa/drivers/dri/i965/brw_state.h | 9 ++++ 2 files changed, 47 insertions(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c index c78e2e3..22ccbfe 100644 --- a/src/mesa/drivers/dri/i965/brw_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c @@ -375,21 +375,16 @@ upload_default_color(struct brw_context *brw, * Sets the sampler state for a single unit based off of the sampler key * entry. */ -static void +void brw_update_sampler_state(struct brw_context *brw, - int unit, + GLenum target, bool tex_cube_map_seamless, + GLfloat tex_unit_lod_bias, + mesa_format format, GLenum base_format, + bool is_integer_format, + const struct gl_sampler_object *sampler, uint32_t *sampler_state, uint32_t batch_offset_for_sampler_state) { - struct gl_context *ctx = &brw->ctx; - const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - const struct gl_texture_object *texObj = texUnit->_Current; - const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); - - /* These don't use samplers at all. */ - if (texObj->Target == GL_TEXTURE_BUFFER) - return; - unsigned min_filter, mag_filter, mip_filter; /* Select min and mip filters. */ @@ -459,12 +454,12 @@ brw_update_sampler_state(struct brw_context *brw, unsigned wrap_t = translate_wrap_mode(brw, sampler->WrapT, either_nearest); unsigned wrap_r = translate_wrap_mode(brw, sampler->WrapR, either_nearest); - if (texObj->Target == GL_TEXTURE_CUBE_MAP || - texObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) { + if (target == GL_TEXTURE_CUBE_MAP || + target == GL_TEXTURE_CUBE_MAP_ARRAY) { /* Cube maps must use the same wrap mode for all three coordinate * dimensions. Prior to Haswell, only CUBE and CLAMP are valid. */ - if ((ctx->Texture.CubeMapSeamless || sampler->CubeMapSeamless) && + if ((tex_cube_map_seamless || sampler->CubeMapSeamless) && (sampler->MinFilter != GL_NEAREST || sampler->MagFilter != GL_NEAREST)) { wrap_s = BRW_TEXCOORDMODE_CUBE; @@ -475,7 +470,7 @@ brw_update_sampler_state(struct brw_context *brw, wrap_t = BRW_TEXCOORDMODE_CLAMP; wrap_r = BRW_TEXCOORDMODE_CLAMP; } - } else if (texObj->Target == GL_TEXTURE_1D) { + } else if (target == GL_TEXTURE_1D) { /* There's a bug in 1D texture sampling - it actually pays * attention to the wrap_t value, though it should not. * Override the wrap_t value here to GL_REPEAT to keep @@ -495,7 +490,7 @@ brw_update_sampler_state(struct brw_context *brw, const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), lod_bits); const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), lod_bits); const int lod_bias = - S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), lod_bits); + S_FIXED(CLAMP(tex_unit_lod_bias + sampler->LodBias, -16, 15), lod_bits); const unsigned base_level = U_FIXED(0, 1); /* Upload the border color if necessary. If not, just point it at @@ -506,14 +501,12 @@ brw_update_sampler_state(struct brw_context *brw, if (wrap_mode_needs_border_color(wrap_s) || wrap_mode_needs_border_color(wrap_t) || wrap_mode_needs_border_color(wrap_r)) { - const struct gl_texture_image *first_image = - texObj->Image[0][texObj->BaseLevel]; upload_default_color(brw, sampler, - first_image->TexFormat, first_image->_BaseFormat, - texObj->_IsIntegerFormat, &border_color_offset); + format, base_format, is_integer_format, + &border_color_offset); } - const bool non_normalized_coords = texObj->Target == GL_TEXTURE_RECTANGLE; + const bool non_normalized_coords = target == GL_TEXTURE_RECTANGLE; brw_emit_sampler_state(brw, sampler_state, @@ -528,6 +521,29 @@ brw_update_sampler_state(struct brw_context *brw, border_color_offset); } +static void +update_sampler_state(struct brw_context *brw, + int unit, + uint32_t *sampler_state, + uint32_t batch_offset_for_sampler_state) +{ + struct gl_context *ctx = &brw->ctx; + const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; + const struct gl_texture_object *texObj = texUnit->_Current; + const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); + + /* These don't use samplers at all. */ + if (texObj->Target == GL_TEXTURE_BUFFER) + return; + + struct gl_texture_image *firstImage = texObj->Image[0][texObj->BaseLevel]; + brw_update_sampler_state(brw, texObj->Target, ctx->Texture.CubeMapSeamless, + texUnit->LodBias, + firstImage->TexFormat, firstImage->_BaseFormat, + texObj->_IsIntegerFormat, + sampler, + sampler_state, batch_offset_for_sampler_state); +} static void brw_upload_sampler_state_table(struct brw_context *brw, @@ -557,7 +573,7 @@ brw_upload_sampler_state_table(struct brw_context *brw, if (SamplersUsed & (1 << s)) { const unsigned unit = prog->SamplerUnits[s]; if (ctx->Texture.Unit[unit]._Current) { - brw_update_sampler_state(brw, unit, sampler_state, + update_sampler_state(brw, unit, sampler_state, batch_offset_for_sampler_state); } } diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 8798369..ab067c3 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -283,6 +283,15 @@ void brw_emit_sampler_state(struct brw_context *brw, bool non_normalized_coordinates, uint32_t border_color_offset); +void brw_update_sampler_state(struct brw_context *brw, + GLenum target, bool tex_cube_map_seamless, + GLfloat tex_unit_lod_bias, + mesa_format format, GLenum base_format, + bool is_integer_format, + const struct gl_sampler_object *sampler, + uint32_t *sampler_state, + uint32_t batch_offset_for_sampler_state); + /* gen6_sf_state.c */ void calculate_attr_overrides(const struct brw_context *brw, From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/blorp: Remove constant parameter Message-ID: <20150429215500.C7E6F761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: d271a13ba31168e0de75d7d4c1d4d7a2e2fb136c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d271a13ba31168e0de75d7d4c1d4d7a2e2fb136c Author: Topi Pohjolainen Date: Sat Mar 14 10:21:33 2015 +0200 i965/blorp: Remove constant parameter This was still needed when we had support for blorp clears but now this is fixed to nop. Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 1 - src/mesa/drivers/dri/i965/brw_blorp.h | 8 -------- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 11 ----------- 3 files changed, 20 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 131e155..b0de55d 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -162,7 +162,6 @@ brw_blorp_params::brw_blorp_params() y1(0), depth_format(0), hiz_op(GEN6_HIZ_OP_NONE), - fast_clear_op(GEN7_FAST_CLEAR_OP_NONE), use_wm_prog(false) { color_write_disable[0] = false; diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index ff68000..59aecab 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -208,13 +208,6 @@ struct brw_blorp_prog_data }; -enum gen7_fast_clear_op { - GEN7_FAST_CLEAR_OP_NONE, - GEN7_FAST_CLEAR_OP_FAST_CLEAR, - GEN7_FAST_CLEAR_OP_RESOLVE, -}; - - class brw_blorp_params { public: @@ -232,7 +225,6 @@ public: brw_blorp_surface_info src; brw_blorp_surface_info dst; enum gen6_hiz_op hiz_op; - enum gen7_fast_clear_op fast_clear_op; bool use_wm_prog; brw_blorp_wm_push_constants wm_push_consts; bool color_write_disable[4]; diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index fb6a0dd..8215fe9 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -529,17 +529,6 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0; } - switch (params->fast_clear_op) { - case GEN7_FAST_CLEAR_OP_FAST_CLEAR: - dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE; - break; - case GEN7_FAST_CLEAR_OP_RESOLVE: - dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE; - break; - default: - break; - } - BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); OUT_BATCH(params->use_wm_prog ? prog_offset : 0); From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/ps: Use SET_FIELD() for sampler count Message-ID: <20150429215500.4EB0D761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: f39846fb57c2b4d29b65a40019ba55219b062117 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f39846fb57c2b4d29b65a40019ba55219b062117 Author: Topi Pohjolainen Date: Wed Apr 29 20:35:45 2015 +0300 i965/ps: Use SET_FIELD() for sampler count The value is actually clamped to 0-16 as sample state pointer can be used to support more than 16 samplers. Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/gen7_wm_state.c | 5 +++-- src/mesa/drivers/dri/i965/gen8_ps_state.c | 5 +++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index bd3218a..7d55d85 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -2259,6 +2259,7 @@ enum brw_wm_barycentric_interp_mode { # define GEN7_PS_SPF_MODE (1 << 31) # define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30) # define GEN7_PS_SAMPLER_COUNT_SHIFT 27 +# define GEN7_PS_SAMPLER_COUNT_MASK INTEL_MASK(29, 27) # define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 # define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 923414e..55a1acd 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -135,8 +135,9 @@ upload_ps_state(struct brw_context *brw) dw2 = dw4 = dw5 = ksp2 = 0; - dw2 |= - (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT; + const unsigned sampler_count = + DIV_ROUND_UP(CLAMP(brw->wm.base.sampler_count, 0, 16), 4); + dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT); dw2 |= ((prog_data->base.binding_table.size_bytes / 4) << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT); diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 5f39e12..8481153 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -133,8 +133,9 @@ upload_ps_state(struct brw_context *brw) */ dw3 |= GEN7_PS_VECTOR_MASK_ENABLE; - dw3 |= - (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT; + const unsigned sampler_count = + DIV_ROUND_UP(CLAMP(brw->wm.base.sampler_count, 0, 16), 4); + dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT); /* BRW_NEW_FS_PROG_DATA */ dw3 |= From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965: Remove dependency to tex object in default color setup Message-ID: <20150429215500.912A4761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 47f32cb50d19145ed502e1fccd949d931c0cd392 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47f32cb50d19145ed502e1fccd949d931c0cd392 Author: Topi Pohjolainen Date: Sat Apr 4 20:28:45 2015 +0300 i965: Remove dependency to tex object in default color setup Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_sampler_state.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c index c4bd949..c78e2e3 100644 --- a/src/mesa/drivers/dri/i965/brw_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c @@ -201,16 +201,13 @@ wrap_mode_needs_border_color(unsigned wrap_mode) static void upload_default_color(struct brw_context *brw, const struct gl_sampler_object *sampler, - int unit, + mesa_format format, GLenum base_format, + bool is_integer_format, uint32_t *sdc_offset) { - struct gl_context *ctx = &brw->ctx; - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *texObj = texUnit->_Current; - struct gl_texture_image *firstImage = texObj->Image[0][texObj->BaseLevel]; union gl_color_union color; - switch (firstImage->_BaseFormat) { + switch (base_format) { case GL_DEPTH_COMPONENT: /* GL specs that border color for depth textures is taken from the * R channel, while the hardware uses A. Spam R into all the @@ -257,7 +254,7 @@ upload_default_color(struct brw_context *brw, * where we've initialized the A channel to 1.0. We also have to set * the border color alpha to 1.0 in that case. */ - if (firstImage->_BaseFormat == GL_RGB) + if (base_format == GL_RGB) color.ui[3] = float_as_int(1.0); if (brw->gen >= 8) { @@ -269,7 +266,7 @@ upload_default_color(struct brw_context *brw, uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR, 4 * 4, 64, sdc_offset); memcpy(sdc, color.ui, 4 * 4); - } else if (brw->is_haswell && texObj->_IsIntegerFormat) { + } else if (brw->is_haswell && is_integer_format) { /* Haswell's integer border color support is completely insane: * SAMPLER_BORDER_COLOR_STATE is 20 DWords. The first four are * for float colors. The next 12 DWords are MBZ and only exist to @@ -283,7 +280,6 @@ upload_default_color(struct brw_context *brw, memset(sdc, 0, 20 * 4); sdc = &sdc[16]; - mesa_format format = firstImage->TexFormat; int bits_per_channel = _mesa_get_format_bits(format, GL_RED_BITS); /* From the Haswell PRM, "Command Reference: Structures", Page 36: @@ -314,7 +310,7 @@ upload_default_color(struct brw_context *brw, ((uint16_t *) sdc)[5] = c[3]; /* A -> DWord 3, bits 31:16 */ break; case 32: - if (firstImage->_BaseFormat == GL_RG) { + if (base_format == GL_RG) { /* Careful inspection of the tables reveals that for RG32 formats, * the green channel needs to go where blue normally belongs. */ @@ -510,7 +506,11 @@ brw_update_sampler_state(struct brw_context *brw, if (wrap_mode_needs_border_color(wrap_s) || wrap_mode_needs_border_color(wrap_t) || wrap_mode_needs_border_color(wrap_r)) { - upload_default_color(brw, sampler, unit, &border_color_offset); + const struct gl_texture_image *first_image = + texObj->Image[0][texObj->BaseLevel]; + upload_default_color(brw, sampler, + first_image->TexFormat, first_image->_BaseFormat, + texObj->_IsIntegerFormat, &border_color_offset); } const bool non_normalized_coords = texObj->Target == GL_TEXTURE_RECTANGLE; From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/ps/gen8: Refactor state uploading Message-ID: <20150429215500.B3135761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: fea168f49584333aeeabad2d2b0dc6aaee86f881 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fea168f49584333aeeabad2d2b0dc6aaee86f881 Author: Topi Pohjolainen Date: Mon Mar 2 12:31:17 2015 +0200 i965/ps/gen8: Refactor state uploading v2: Use SET_FIELD() for sampler count, and for that reason added GEN7_PS_SAMPLER_COUNT_MASK. Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 12 +++++ src/mesa/drivers/dri/i965/gen8_ps_state.c | 72 ++++++++++++++++++----------- 2 files changed, 58 insertions(+), 26 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index f8d56b9..13d541b 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -265,6 +265,18 @@ void gen7_set_surface_mcs_info(struct brw_context *brw, void gen7_check_surface_setup(uint32_t *surf, bool is_render_target); void gen7_init_vtable_surface_functions(struct brw_context *brw); +/* gen8_ps_state.c */ +void gen8_upload_ps_state(struct brw_context *brw, + const struct gl_fragment_program *fp, + const struct brw_stage_state *stage_state, + const struct brw_wm_prog_data *prog_data, + uint32_t fast_clear_op); + +void gen8_upload_ps_extra(struct brw_context *brw, + const struct gl_fragment_program *fp, + const struct brw_wm_prog_data *prog_data, + bool multisampled_fbo); + /* gen7_sol_state.c */ void gen7_upload_3dstate_so_decl_list(struct brw_context *brw, const struct brw_vue_map *vue_map); diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 8481153..85ad3b6 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -27,15 +27,13 @@ #include "brw_defines.h" #include "intel_batchbuffer.h" -static void -upload_ps_extra(struct brw_context *brw) +void +gen8_upload_ps_extra(struct brw_context *brw, + const struct gl_fragment_program *fp, + const struct brw_wm_prog_data *prog_data, + bool multisampled_fbo) { struct gl_context *ctx = &brw->ctx; - /* BRW_NEW_FRAGMENT_PROGRAM */ - const struct brw_fragment_program *fp = - brw_fragment_program_const(brw->fragment_program); - /* BRW_NEW_FS_PROG_DATA */ - const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; uint32_t dw1 = 0; dw1 |= GEN8_PSX_PIXEL_SHADER_VALID; @@ -47,16 +45,14 @@ upload_ps_extra(struct brw_context *brw) if (prog_data->num_varying_inputs != 0) dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE; - if (fp->program.Base.InputsRead & VARYING_BIT_POS) + if (fp->Base.InputsRead & VARYING_BIT_POS) dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W; - /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */ - bool multisampled_fbo = brw->num_samples > 1; if (multisampled_fbo && - _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1) + _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1) dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE; - if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) + if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK; if (prog_data->uses_omask) @@ -68,6 +64,20 @@ upload_ps_extra(struct brw_context *brw) ADVANCE_BATCH(); } +static void +upload_ps_extra(struct brw_context *brw) +{ + /* BRW_NEW_FRAGMENT_PROGRAM */ + const struct brw_fragment_program *fp = + brw_fragment_program_const(brw->fragment_program); + /* BRW_NEW_FS_PROG_DATA */ + const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; + /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */ + const bool multisampled_fbo = brw->num_samples > 1; + + gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo); +} + const struct brw_tracked_state gen8_ps_extra = { .dirty = { .mesa = _NEW_MULTISAMPLE, @@ -118,15 +128,16 @@ const struct brw_tracked_state gen8_wm_state = { .emit = upload_wm_state, }; -static void -upload_ps_state(struct brw_context *brw) +void +gen8_upload_ps_state(struct brw_context *brw, + const struct gl_fragment_program *fp, + const struct brw_stage_state *stage_state, + const struct brw_wm_prog_data *prog_data, + uint32_t fast_clear_op) { struct gl_context *ctx = &brw->ctx; uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0; - /* BRW_NEW_FS_PROG_DATA */ - const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; - /* Initialize the execution mask with VMask. Otherwise, derivatives are * incorrect for subspans where some of the pixels are unlit. We believe * the bit just didn't take effect in previous generations. @@ -134,7 +145,7 @@ upload_ps_state(struct brw_context *brw) dw3 |= GEN7_PS_VECTOR_MASK_ENABLE; const unsigned sampler_count = - DIV_ROUND_UP(CLAMP(brw->wm.base.sampler_count, 0, 16), 4); + DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT); /* BRW_NEW_FS_PROG_DATA */ @@ -171,12 +182,12 @@ upload_ps_state(struct brw_context *brw) * We only require XY sample offsets. So, this recommendation doesn't * look useful at the moment. We might need this in future. */ - if (brw->wm.prog_data->uses_pos_offset) + if (prog_data->uses_pos_offset) dw6 |= GEN7_PS_POSOFFSET_SAMPLE; else dw6 |= GEN7_PS_POSOFFSET_NONE; - dw6 |= brw->wm.fast_clear_op; + dw6 |= fast_clear_op; /* _NEW_MULTISAMPLE * In case of non 1x per sample shading, only one of SIMD8 and SIMD16 @@ -185,7 +196,7 @@ upload_ps_state(struct brw_context *brw) * better performance than 'SIMD8 only' dispatch. */ int min_invocations_per_fragment = - _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false); + _mesa_get_min_invocations_per_fragment(ctx, fp, false); assert(min_invocations_per_fragment >= 1); if (prog_data->prog_offset_16 || prog_data->no_8) { @@ -196,19 +207,19 @@ upload_ps_state(struct brw_context *brw) GEN7_PS_DISPATCH_START_GRF_SHIFT_0); dw7 |= (prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2); - ksp0 = brw->wm.base.prog_offset; - ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16; + ksp0 = stage_state->prog_offset; + ksp2 = stage_state->prog_offset + prog_data->prog_offset_16; } else { dw7 |= (prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); - ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16; + ksp0 = stage_state->prog_offset + prog_data->prog_offset_16; } } else { dw6 |= GEN7_PS_8_DISPATCH_ENABLE; dw7 |= (prog_data->base.dispatch_grf_start_reg << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); - ksp0 = brw->wm.base.prog_offset; + ksp0 = stage_state->prog_offset; } BEGIN_BATCH(12); @@ -217,7 +228,7 @@ upload_ps_state(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(dw3); if (prog_data->base.total_scratch) { - OUT_RELOC64(brw->wm.base.scratch_bo, + OUT_RELOC64(stage_state->scratch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, ffs(prog_data->base.total_scratch) - 11); } else { @@ -233,6 +244,15 @@ upload_ps_state(struct brw_context *brw) ADVANCE_BATCH(); } +static void +upload_ps_state(struct brw_context *brw) +{ + /* BRW_NEW_FS_PROG_DATA */ + const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; + gen8_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data, + brw->wm.fast_clear_op); +} + const struct brw_tracked_state gen8_ps_state = { .dirty = { .mesa = _NEW_MULTISAMPLE, From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/gen7/blorp: Remove unused arguments Message-ID: <20150429215500.E913E761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: dce1972945a4568c181011880e0336a2a14909ec URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dce1972945a4568c181011880e0336a2a14909ec Author: Topi Pohjolainen Date: Fri Jan 30 11:30:34 2015 +0200 i965/gen7/blorp: Remove unused arguments Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 75 +++++++++++------------------- 1 file changed, 28 insertions(+), 47 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index d841346..c9e7cb7 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -48,8 +48,7 @@ * valid. */ static void -gen7_blorp_emit_urb_config(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_urb_config(struct brw_context *brw) { unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16; gen7_emit_push_constant_state(brw, @@ -73,7 +72,6 @@ gen7_blorp_emit_urb_config(struct brw_context *brw, /* 3DSTATE_BLEND_STATE_POINTERS */ static void gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, - const brw_blorp_params *params, uint32_t cc_blend_state_offset) { BEGIN_BATCH(2); @@ -86,7 +84,6 @@ gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, /* 3DSTATE_CC_STATE_POINTERS */ static void gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, - const brw_blorp_params *params, uint32_t cc_state_offset) { BEGIN_BATCH(2); @@ -96,8 +93,7 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, } static void -gen7_blorp_emit_cc_viewport(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_cc_viewport(struct brw_context *brw) { struct brw_cc_viewport *ccv; uint32_t cc_vp_offset; @@ -121,7 +117,6 @@ gen7_blorp_emit_cc_viewport(struct brw_context *brw, */ static void gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, - const brw_blorp_params *params, uint32_t depthstencil_offset) { BEGIN_BATCH(2); @@ -136,7 +131,6 @@ gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, */ static uint32_t gen7_blorp_emit_surface_state(struct brw_context *brw, - const brw_blorp_params *params, const brw_blorp_surface_info *surface, uint32_t read_domains, uint32_t write_domain, bool is_render_target) @@ -228,8 +222,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, * Disable vertex shader. */ static void -gen7_blorp_emit_vs_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_vs_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); @@ -257,8 +250,7 @@ gen7_blorp_emit_vs_disable(struct brw_context *brw, * Disable the hull shader. */ static void -gen7_blorp_emit_hs_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_hs_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2)); @@ -287,8 +279,7 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw, * Disable the tesselation engine. */ static void -gen7_blorp_emit_te_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_te_disable(struct brw_context *brw) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2)); @@ -304,8 +295,7 @@ gen7_blorp_emit_te_disable(struct brw_context *brw, * Disable the domain shader. */ static void -gen7_blorp_emit_ds_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_ds_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2)); @@ -332,8 +322,7 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw, * Disable the geometry shader. */ static void -gen7_blorp_emit_gs_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_gs_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2)); @@ -377,8 +366,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw, * Disable streamout. */ static void -gen7_blorp_emit_streamout_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_streamout_disable(struct brw_context *brw) { BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2)); @@ -544,7 +532,6 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, static void gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, - const brw_blorp_params *params, uint32_t wm_bind_bo_offset) { BEGIN_BATCH(2); @@ -556,7 +543,6 @@ gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, static void gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, - const brw_blorp_params *params, uint32_t sampler_offset) { BEGIN_BATCH(2); @@ -568,7 +554,6 @@ gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, static void gen7_blorp_emit_constant_ps(struct brw_context *brw, - const brw_blorp_params *params, uint32_t wm_push_const_offset) { const uint8_t mocs = GEN7_MOCS_L3; @@ -595,8 +580,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw, } static void -gen7_blorp_emit_constant_ps_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_constant_ps_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2)); @@ -708,8 +692,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, static void -gen7_blorp_emit_depth_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_depth_disable(struct brw_context *brw) { intel_emit_depth_stall_flushes(brw); @@ -800,29 +783,28 @@ gen7_blorp_exec(struct brw_context *brw, (1 << params->dst.num_samples) - 1 : 1); gen6_blorp_emit_state_base_address(brw, params); gen6_blorp_emit_vertices(brw, params); - gen7_blorp_emit_urb_config(brw, params); + gen7_blorp_emit_urb_config(brw); if (params->use_wm_prog) { cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); cc_state_offset = gen6_blorp_emit_cc_state(brw, params); - gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset); - gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset); + gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset); + gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset); } depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params); - gen7_blorp_emit_depth_stencil_state_pointers(brw, params, - depthstencil_offset); + gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset); if (params->use_wm_prog) { uint32_t wm_surf_offset_renderbuffer; uint32_t wm_surf_offset_texture = 0; wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); intel_miptree_used_for_rendering(params->dst.mt); wm_surf_offset_renderbuffer = - gen7_blorp_emit_surface_state(brw, params, ¶ms->dst, + gen7_blorp_emit_surface_state(brw, ¶ms->dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, true /* is_render_target */); if (params->src.mt) { wm_surf_offset_texture = - gen7_blorp_emit_surface_state(brw, params, ¶ms->src, + gen7_blorp_emit_surface_state(brw, ¶ms->src, I915_GEM_DOMAIN_SAMPLER, 0, false /* is_render_target */); } @@ -833,30 +815,29 @@ gen7_blorp_exec(struct brw_context *brw, sampler_offset = gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true); } - gen7_blorp_emit_vs_disable(brw, params); - gen7_blorp_emit_hs_disable(brw, params); - gen7_blorp_emit_te_disable(brw, params); - gen7_blorp_emit_ds_disable(brw, params); - gen7_blorp_emit_gs_disable(brw, params); - gen7_blorp_emit_streamout_disable(brw, params); + gen7_blorp_emit_vs_disable(brw); + gen7_blorp_emit_hs_disable(brw); + gen7_blorp_emit_te_disable(brw); + gen7_blorp_emit_ds_disable(brw); + gen7_blorp_emit_gs_disable(brw); + gen7_blorp_emit_streamout_disable(brw); gen6_blorp_emit_clip_disable(brw, params); gen7_blorp_emit_sf_config(brw, params); gen7_blorp_emit_wm_config(brw, params, prog_data); if (params->use_wm_prog) { - gen7_blorp_emit_binding_table_pointers_ps(brw, params, - wm_bind_bo_offset); - gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset); - gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset); + gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset); + gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset); + gen7_blorp_emit_constant_ps(brw, wm_push_const_offset); } else { - gen7_blorp_emit_constant_ps_disable(brw, params); + gen7_blorp_emit_constant_ps_disable(brw); } gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data); - gen7_blorp_emit_cc_viewport(brw, params); + gen7_blorp_emit_cc_viewport(brw); if (params->depth.mt) gen7_blorp_emit_depth_stencil_config(brw, params); else - gen7_blorp_emit_depth_disable(brw, params); + gen7_blorp_emit_depth_disable(brw); gen7_blorp_emit_clear_params(brw, params); gen6_blorp_emit_drawing_rectangle(brw, params); gen7_blorp_emit_primitive(brw, params); From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:01 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:01 -0700 (PDT) Subject: Mesa (master): i965/blorp: Allow blend state to be set for multiple render targets Message-ID: <20150429215501.15EBB761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 91daf9f09bac41c84c6868a56e0d538cc59cc334 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=91daf9f09bac41c84c6868a56e0d538cc59cc334 Author: Topi Pohjolainen Date: Thu Mar 26 16:43:31 2015 +0200 i965/blorp: Allow blend state to be set for multiple render targets Original blorp writes only one buffer per shader invocation. Once the launch mechanism is shared with glsl-based programs there will be need for supporting multiple render targets. Also drop the always constant color write disable settings. Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 ++++------ src/mesa/drivers/dri/i965/brw_blorp.h | 5 +++-- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 +++++++++++----------- 3 files changed, 18 insertions(+), 19 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 0c0cd2b..8f82851 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -155,7 +155,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, } -brw_blorp_params::brw_blorp_params(unsigned num_varyings) +brw_blorp_params::brw_blorp_params(unsigned num_varyings, + unsigned num_draw_buffers) : x0(0), y0(0), x1(0), @@ -163,12 +164,9 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings) depth_format(0), hiz_op(GEN6_HIZ_OP_NONE), use_wm_prog(false), - num_varyings(num_varyings) + num_varyings(num_varyings), + num_draw_buffers(num_draw_buffers) { - color_write_disable[0] = false; - color_write_disable[1] = false; - color_write_disable[2] = false; - color_write_disable[3] = false; } extern "C" { diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 0ba3891..c9957a6 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -211,7 +211,8 @@ struct brw_blorp_prog_data class brw_blorp_params { public: - explicit brw_blorp_params(unsigned num_varyings = 0); + brw_blorp_params(unsigned num_varyings = 0, + unsigned num_draw_buffers = 1); virtual uint32_t get_wm_prog(struct brw_context *brw, brw_blorp_prog_data **prog_data) const = 0; @@ -227,8 +228,8 @@ public: enum gen6_hiz_op hiz_op; bool use_wm_prog; brw_blorp_wm_push_constants wm_push_consts; - bool color_write_disable[4]; const unsigned num_varyings; + const unsigned num_draw_buffers; }; diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 405a3e8..bfd2001 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -246,21 +246,21 @@ gen6_blorp_emit_blend_state(struct brw_context *brw, { uint32_t cc_blend_state_offset; + assume(params->num_draw_buffers); + + const unsigned size = params->num_draw_buffers * + sizeof(struct gen6_blend_state); struct gen6_blend_state *blend = (struct gen6_blend_state *) - brw_state_batch(brw, AUB_TRACE_BLEND_STATE, - sizeof(struct gen6_blend_state), 64, + brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64, &cc_blend_state_offset); - memset(blend, 0, sizeof(*blend)); - - blend->blend1.pre_blend_clamp_enable = 1; - blend->blend1.post_blend_clamp_enable = 1; - blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; + memset(blend, 0, size); - blend->blend1.write_disable_r = params->color_write_disable[0]; - blend->blend1.write_disable_g = params->color_write_disable[1]; - blend->blend1.write_disable_b = params->color_write_disable[2]; - blend->blend1.write_disable_a = params->color_write_disable[3]; + for (unsigned i = 0; i < params->num_draw_buffers; ++i) { + blend[i].blend1.pre_blend_clamp_enable = 1; + blend[i].blend1.post_blend_clamp_enable = 1; + blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; + } return cc_blend_state_offset; } From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:01 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:01 -0700 (PDT) Subject: Mesa (master): i965/blorp: Prepare drawing rectangle for flipped coordinates Message-ID: <20150429215501.2C61F761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 13670e8bade296c5c5846dc08615563ad51685e4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13670e8bade296c5c5846dc08615563ad51685e4 Author: Topi Pohjolainen Date: Sun Mar 29 21:52:02 2015 +0300 i965/blorp: Prepare drawing rectangle for flipped coordinates Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index ed08898..b6a3d78 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -950,8 +950,8 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); OUT_BATCH(0); - OUT_BATCH(((params->x1 - 1) & 0xffff) | - ((params->y1 - 1) << 16)); + OUT_BATCH(((MAX2(params->x1, params->x0) - 1) & 0xffff) | + ((MAX2(params->y1, params->y0) - 1) << 16)); OUT_BATCH(0); ADVANCE_BATCH(); } From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965: Refactor rb surface setup to allow caller to store offsets Message-ID: <20150429215500.6BC0B761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea Author: Topi Pohjolainen Date: Tue Mar 17 13:09:16 2015 +0200 i965: Refactor rb surface setup to allow caller to store offsets Notice that in gen7_wm_surface_state.c there is also indentation change in the surrounding code removing tabs. v2 (Matt): Fixed whitespace: tabs -> spaces Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 8 ++--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 38 +++++++++++---------- src/mesa/drivers/dri/i965/gen6_surface_state.c | 25 +++++++------- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 28 +++++++-------- src/mesa/drivers/dri/i965/gen8_surface_state.c | 18 +++++----- 5 files changed, 59 insertions(+), 58 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 8db1028..e2f26f5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -967,10 +967,10 @@ struct brw_context unsigned unit, uint32_t *surf_offset, bool for_gather); - void (*update_renderbuffer_surface)(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, - unsigned unit); + uint32_t (*update_renderbuffer_surface)(struct brw_context *brw, + struct gl_renderbuffer *rb, + bool layered, unsigned unit, + uint32_t surf_index); void (*emit_texture_surface_state)(struct brw_context *brw, struct intel_mipmap_tree *mt, diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 161d140..d451940 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -626,11 +626,11 @@ brw_emit_null_surface_state(struct brw_context *brw, * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t brw_update_renderbuffer_surface(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, - unsigned int unit) + struct gl_renderbuffer *rb, + bool layered, unsigned unit, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); @@ -638,11 +638,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw, uint32_t *surf; uint32_t tile_x, tile_y; uint32_t format = 0; + uint32_t offset; /* _NEW_BUFFERS */ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); /* BRW_NEW_FS_PROG_DATA */ - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; assert(!layered); @@ -663,8 +662,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, intel_miptree_used_for_rendering(irb->mt); - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, - &brw->wm.base.surf_offset[surf_index]); + surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset); format = brw->render_target_format[rb_format]; if (unlikely(!brw->format_supported_as_render_target[rb_format])) { @@ -721,11 +719,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw, } drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 4, - mt->bo, - surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + offset + 4, + mt->bo, + surf[1] - mt->bo->offset64, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); + + return offset; } /** @@ -743,13 +743,15 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw) /* Update surfaces for drawing buffers */ if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { + const uint32_t surf_index = + brw->wm.prog_data->binding_table.render_target_start + i; + if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { - brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], - ctx->DrawBuffer->MaxNumLayers > 0, i); + brw->wm.base.surf_offset[surf_index] = + brw->vtbl.update_renderbuffer_surface( + brw, ctx->DrawBuffer->_ColorDrawBuffers[i], + ctx->DrawBuffer->MaxNumLayers > 0, i, surf_index); } else { - const uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + i; - brw->vtbl.emit_null_surface_state( brw, fb->Width, fb->Height, fb->Visual.samples, &brw->wm.base.surf_offset[surf_index]); diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c index fadc353..03e913a 100644 --- a/src/mesa/drivers/dri/i965/gen6_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c @@ -45,17 +45,18 @@ * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t gen6_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, - bool layered, - unsigned int unit) + bool layered, unsigned unit /* unused */, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; uint32_t *surf; uint32_t format = 0; + uint32_t offset; /* _NEW_BUFFERS */ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); uint32_t surftype; @@ -63,13 +64,9 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, const GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; - intel_miptree_used_for_rendering(irb->mt); - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, - &brw->wm.base.surf_offset[surf_index]); + surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset); format = brw->render_target_format[rb_format]; if (unlikely(!brw->format_supported_as_render_target[rb_format])) { @@ -131,11 +128,13 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0); drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 4, - mt->bo, - surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + offset + 4, + mt->bo, + surf[1] - mt->bo->offset64, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); + + return offset; } void diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 4b8503c..15ab2b0 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -448,11 +448,11 @@ gen7_emit_null_surface_state(struct brw_context *brw, * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t gen7_update_renderbuffer_surface(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, - unsigned int unit) + struct gl_renderbuffer *rb, + bool layered, unsigned unit /* unused */, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); @@ -464,17 +464,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, bool is_array = false; int depth = MAX2(irb->layer_count, 1); const uint8_t mocs = GEN7_MOCS_L3; + uint32_t offset; int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1); GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, - &brw->wm.base.surf_offset[surf_index]); + &offset); memset(surf, 0, 8 * 4); intel_miptree_used_for_rendering(irb->mt); @@ -539,7 +537,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT; if (irb->mt->mcs_mt) { - gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index], + gen7_set_surface_mcs_info(brw, surf, offset, irb->mt->mcs_mt, true /* is RT */); } @@ -553,13 +551,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, } drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 4, - mt->bo, - surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + offset + 4, + mt->bo, + surf[1] - mt->bo->offset64, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); gen7_check_surface_setup(surf, true /* is_render_target */); + + return offset; } void diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index f347065..d0c2d80 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -324,11 +324,11 @@ gen8_emit_null_surface_state(struct brw_context *brw, * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t gen8_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, - bool layered, - unsigned unit) + bool layered, unsigned unit /* unused */, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); @@ -341,14 +341,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, uint32_t tiling = mt->tiling; uint32_t format = 0; uint32_t surf_type; + uint32_t offset; bool is_array = false; int depth = MAX2(irb->layer_count, 1); const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ? irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1)); GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; /* FINISHME: Use PTE MOCS on Skylake. */ uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_WT : BDW_MOCS_PTE; @@ -393,8 +392,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, aux_mode = GEN8_SURFACE_AUX_MODE_MCS; } - uint32_t *surf = - allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]); + uint32_t *surf = allocate_surface_state(brw, &offset); surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) | (is_array ? GEN7_SURFACE_IS_ARRAY : 0) | @@ -439,7 +437,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, if (aux_mt) { *((uint64_t *) &surf[10]) = aux_mt->bo->offset64; drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 10 * 4, + offset + 10 * 4, aux_mt->bo, 0, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); } else { @@ -449,11 +447,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, surf[12] = 0; drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 8 * 4, + offset + 8 * 4, mt->bo, mt->offset, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); + + return offset; } void From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965: Refactor and expose brw_upload_binding_table() Message-ID: <20150429215500.84312761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 21071afc431bb17419c353151544518be7daf05f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21071afc431bb17419c353151544518be7daf05f Author: Topi Pohjolainen Date: Thu Mar 19 10:42:49 2015 +0200 i965: Refactor and expose brw_upload_binding_table() Read and write parts of the state stage are also split into explicit arguments allowing future patches to use constant program data. v2 (Ken): s/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/ Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 21 ++++++++++++++------- src/mesa/drivers/dri/i965/brw_state.h | 7 +++++++ 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c index 459165a..98ff0dd 100644 --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c @@ -50,15 +50,13 @@ * This copies brw_stage_state::surf_offset[] into the indirect state section * of the batchbuffer (allocated by brw_state_batch()). */ -static void +void brw_upload_binding_table(struct brw_context *brw, uint32_t packet_name, GLbitfield brw_new_binding_table, + const struct brw_stage_prog_data *prog_data, struct brw_stage_state *stage_state) { - /* BRW_NEW_*_PROG_DATA */ - struct brw_stage_prog_data *prog_data = stage_state->prog_data; - if (prog_data->binding_table.size_bytes == 0) { /* There are no surfaces; skip making the binding table altogether. */ if (stage_state->bind_bo_offset == 0 && brw->gen < 9) @@ -103,9 +101,12 @@ brw_upload_binding_table(struct brw_context *brw, static void brw_vs_upload_binding_table(struct brw_context *brw) { + /* BRW_NEW_VS_PROG_DATA */ + const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data; brw_upload_binding_table(brw, _3DSTATE_BINDING_TABLE_POINTERS_VS, - BRW_NEW_VS_BINDING_TABLE, &brw->vs.base); + BRW_NEW_VS_BINDING_TABLE, prog_data, + &brw->vs.base); } const struct brw_tracked_state brw_vs_binding_table = { @@ -124,9 +125,12 @@ const struct brw_tracked_state brw_vs_binding_table = { static void brw_upload_wm_binding_table(struct brw_context *brw) { + /* BRW_NEW_FS_PROG_DATA */ + const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data; brw_upload_binding_table(brw, _3DSTATE_BINDING_TABLE_POINTERS_PS, - BRW_NEW_PS_BINDING_TABLE, &brw->wm.base); + BRW_NEW_PS_BINDING_TABLE, prog_data, + &brw->wm.base); } const struct brw_tracked_state brw_wm_binding_table = { @@ -147,9 +151,12 @@ brw_gs_upload_binding_table(struct brw_context *brw) if (brw->geometry_program == NULL) return; + /* BRW_NEW_GS_PROG_DATA */ + const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data; brw_upload_binding_table(brw, _3DSTATE_BINDING_TABLE_POINTERS_GS, - BRW_NEW_GS_BINDING_TABLE, &brw->gs.base); + BRW_NEW_GS_BINDING_TABLE, prog_data, + &brw->gs.base); } const struct brw_tracked_state brw_gs_binding_table = { diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 83058b9..8798369 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -159,6 +159,13 @@ brw_state_dirty(struct brw_context *brw, GLuint mesa_flags, uint64_t brw_flags) (brw->ctx.NewDriverState & brw_flags)) != 0; } +/* brw_binding_tables.c */ +void brw_upload_binding_table(struct brw_context *brw, + uint32_t packet_name, + GLbitfield brw_new_binding_table, + const struct brw_stage_prog_data *prog_data, + struct brw_stage_state *stage_state); + /* brw_misc_state.c */ void brw_upload_invariant_state(struct brw_context *brw); uint32_t From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/blorp: Allow caller to provide sampler settings Message-ID: <20150429215500.DEF64761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 4de0bef7f438147091a7489728c4d187c6efbbc3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4de0bef7f438147091a7489728c4d187c6efbbc3 Author: Topi Pohjolainen Date: Fri Feb 27 21:59:56 2015 +0200 i965/blorp: Allow caller to provide sampler settings v2 (Ken): s/use_unorm_coords/non_normalized_coords/ Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 4 +++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +++++++++------ src/mesa/drivers/dri/i965/gen7_blorp.cpp | 3 ++- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 59aecab..6aaae65 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -415,7 +415,9 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, uint32_t gen6_blorp_emit_sampler_state(struct brw_context *brw, - const brw_blorp_params *params); + unsigned tex_filter, unsigned max_lod, + bool non_normalized_coords); + /** \} */ #endif /* __cplusplus */ diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 6c139ec..14e073b 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -455,7 +455,8 @@ gen6_blorp_emit_binding_table(struct brw_context *brw, */ uint32_t gen6_blorp_emit_sampler_state(struct brw_context *brw, - const brw_blorp_params *params) + unsigned tex_filter, unsigned max_lod, + bool non_normalized_coords) { uint32_t sampler_offset; uint32_t *sampler_state = (uint32_t *) @@ -476,8 +477,8 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw, brw_emit_sampler_state(brw, sampler_state, sampler_offset, - BRW_MAPFILTER_LINEAR, /* min filter */ - BRW_MAPFILTER_LINEAR, /* mag filter */ + tex_filter, /* min filter */ + tex_filter, /* mag filter */ BRW_MIPFILTER_NONE, BRW_ANISORATIO_2, address_rounding, @@ -485,11 +486,11 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw, BRW_TEXCOORDMODE_CLAMP, BRW_TEXCOORDMODE_CLAMP, 0, /* min LOD */ - 0, /* max LOD */ + max_lod, 0, /* LOD bias */ 0, /* base miplevel */ 0, /* shadow function */ - true, /* non-normalized coordinates */ + non_normalized_coords, 0); /* border color offset - unused */ return sampler_offset; @@ -1059,7 +1060,9 @@ gen6_blorp_exec(struct brw_context *brw, gen6_blorp_emit_binding_table(brw, params, wm_surf_offset_renderbuffer, wm_surf_offset_texture); - sampler_offset = gen6_blorp_emit_sampler_state(brw, params); + sampler_offset = + gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true); + gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset); } gen6_blorp_emit_vs_disable(brw, params); diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 8215fe9..d841346 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -830,7 +830,8 @@ gen7_blorp_exec(struct brw_context *brw, gen6_blorp_emit_binding_table(brw, params, wm_surf_offset_renderbuffer, wm_surf_offset_texture); - sampler_offset = gen6_blorp_emit_sampler_state(brw, params); + sampler_offset = + gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true); } gen7_blorp_emit_vs_disable(brw, params); gen7_blorp_emit_hs_disable(brw, params); From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:01 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:01 -0700 (PDT) Subject: Mesa (master): i965/blorp: Prepare for attributes other than render position Message-ID: <20150429215501.09A50761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 7fb0db4dd18e49d3ccdb872f7ed174740301f3a2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7fb0db4dd18e49d3ccdb872f7ed174740301f3a2 Author: Topi Pohjolainen Date: Fri Feb 27 11:45:34 2015 +0200 i965/blorp: Prepare for attributes other than render position Note that the magic number of one in gen7 logic is replaced by BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity. On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET) has no effect for native blorp as blorp doesn't use any additional attributes. In fact, regular pipeline setup always uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional attributes. Hence the change makes the two (blorp and regular) consistent. Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 5 +++-- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 +++-- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 ++++-- 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index b0de55d..0c0cd2b 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -155,14 +155,15 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, } -brw_blorp_params::brw_blorp_params() +brw_blorp_params::brw_blorp_params(unsigned num_varyings) : x0(0), y0(0), x1(0), y1(0), depth_format(0), hiz_op(GEN6_HIZ_OP_NONE), - use_wm_prog(false) + use_wm_prog(false), + num_varyings(num_varyings) { color_write_disable[0] = false; color_write_disable[1] = false; diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index f277dee..0ba3891 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -211,7 +211,7 @@ struct brw_blorp_prog_data class brw_blorp_params { public: - brw_blorp_params(); + explicit brw_blorp_params(unsigned num_varyings = 0); virtual uint32_t get_wm_prog(struct brw_context *brw, brw_blorp_prog_data **prog_data) const = 0; @@ -228,6 +228,7 @@ public: bool use_wm_prog; brw_blorp_wm_push_constants wm_push_consts; bool color_write_disable[4]; + const unsigned num_varyings; }; diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 2fe2840..405a3e8 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -634,9 +634,10 @@ gen6_blorp_emit_sf_config(struct brw_context *brw, { BEGIN_BATCH(20); OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2)); - OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */ + OUT_BATCH(params->num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT | 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT | - 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT); + BRW_SF_URB_ENTRY_READ_OFFSET << + GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT); OUT_BATCH(0); /* dw2 */ OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); for (int i = 0; i < 16; ++i) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 12f515d..3065a4c 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -415,9 +415,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw, { BEGIN_BATCH(14); OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2)); - OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */ + OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE | + params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT | 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | - 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT); + BRW_SF_URB_ENTRY_READ_OFFSET << + GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT); for (int i = 0; i < 12; ++i) OUT_BATCH(0); ADVANCE_BATCH(); From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/gen8: Use constant pointers for reading miptree details Message-ID: <20150429215500.5F0FE761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: d6c83c9d863f9f13e46584b93cbab6d3a3885aea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6c83c9d863f9f13e46584b93cbab6d3a3885aea Author: Topi Pohjolainen Date: Sun Mar 1 22:23:33 2015 +0200 i965/gen8: Use constant pointers for reading miptree details Reviewed-by: Matt Turner Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index b8ef353..f347065 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -70,7 +70,7 @@ surface_tiling_mode(uint32_t tiling) } static unsigned -vertical_alignment(struct intel_mipmap_tree *mt) +vertical_alignment(const struct intel_mipmap_tree *mt) { switch (mt->align_h) { case 4: @@ -85,7 +85,7 @@ vertical_alignment(struct intel_mipmap_tree *mt) } static unsigned -horizontal_alignment(struct intel_mipmap_tree *mt) +horizontal_alignment(const struct intel_mipmap_tree *mt) { switch (mt->align_w) { case 4: From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/ps/gen7: Refactor state uploading Message-ID: <20150429215500.A904C761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 4047420ec47488f2cdd7511cbeea95201b620480 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4047420ec47488f2cdd7511cbeea95201b620480 Author: Topi Pohjolainen Date: Fri Feb 13 11:20:05 2015 +0200 i965/ps/gen7: Refactor state uploading Now the uploading depends only on the input parameters instead of consulting the current gl-state. v2: Rebased on top of sampler count clamping Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 9 +++++ src/mesa/drivers/dri/i965/gen7_wm_state.c | 56 ++++++++++++++++++----------- 2 files changed, 45 insertions(+), 20 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index ab067c3..f8d56b9 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -245,6 +245,15 @@ void brw_update_renderbuffer_surfaces(struct brw_context *brw, uint32_t render_target_start, uint32_t *surf_offset); +/* gen7_wm_state.c */ +void +gen7_upload_ps_state(struct brw_context *brw, + const struct gl_fragment_program *fp, + const struct brw_stage_state *stage_state, + const struct brw_wm_prog_data *prog_data, + bool enable_dual_src_blend, unsigned sample_mask, + unsigned fast_clear_op); + /* gen7_wm_surface_state.c */ uint32_t gen7_surface_tiling_mode(uint32_t tiling); uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout l); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 55a1acd..b918275 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -122,21 +122,23 @@ const struct brw_tracked_state gen7_wm_state = { .emit = upload_wm_state, }; -static void -upload_ps_state(struct brw_context *brw) +void +gen7_upload_ps_state(struct brw_context *brw, + const struct gl_fragment_program *fp, + const struct brw_stage_state *stage_state, + const struct brw_wm_prog_data *prog_data, + bool enable_dual_src_blend, unsigned sample_mask, + unsigned fast_clear_op) { struct gl_context *ctx = &brw->ctx; uint32_t dw2, dw4, dw5, ksp0, ksp2; const int max_threads_shift = brw->is_haswell ? HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; - /* BRW_NEW_FS_PROG_DATA */ - const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; - dw2 = dw4 = dw5 = ksp2 = 0; const unsigned sampler_count = - DIV_ROUND_UP(CLAMP(brw->wm.base.sampler_count, 0, 16), 4); + DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT); dw2 |= ((prog_data->base.binding_table.size_bytes / 4) << @@ -149,7 +151,7 @@ upload_ps_state(struct brw_context *brw) * in 3DSTATE_SAMPLE_MASK; the values should match. */ /* _NEW_BUFFERS, _NEW_MULTISAMPLE */ if (brw->is_haswell) - dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK); + dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK); dw4 |= (brw->max_wm_threads - 1) << max_threads_shift; @@ -182,16 +184,11 @@ upload_ps_state(struct brw_context *brw) else dw4 |= GEN7_PS_POSOFFSET_NONE; - /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR - * - * The hardware wedges if you have this bit set but don't turn on any dual + /* The hardware wedges if you have this bit set but don't turn on any dual * source blend factors. */ - if (prog_data->dual_src_blend && - (ctx->Color.BlendEnabled & 1) && - ctx->Color.Blend[0]._UsesDualSrc) { + if (enable_dual_src_blend) dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE; - } /* BRW_NEW_FS_PROG_DATA */ if (prog_data->num_varying_inputs != 0) @@ -203,7 +200,7 @@ upload_ps_state(struct brw_context *brw) * better performance than 'SIMD8 only' dispatch. */ int min_inv_per_frag = - _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false); + _mesa_get_min_invocations_per_fragment(ctx, fp, false); assert(min_inv_per_frag >= 1); if (prog_data->prog_offset_16 || prog_data->no_8) { @@ -214,22 +211,22 @@ upload_ps_state(struct brw_context *brw) GEN7_PS_DISPATCH_START_GRF_SHIFT_0); dw5 |= (prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2); - ksp0 = brw->wm.base.prog_offset; - ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16; + ksp0 = stage_state->prog_offset; + ksp2 = stage_state->prog_offset + prog_data->prog_offset_16; } else { dw5 |= (prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); - ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16; + ksp0 = stage_state->prog_offset + prog_data->prog_offset_16; } } else { dw4 |= GEN7_PS_8_DISPATCH_ENABLE; dw5 |= (prog_data->base.dispatch_grf_start_reg << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); - ksp0 = brw->wm.base.prog_offset; + ksp0 = stage_state->prog_offset; } - dw4 |= brw->wm.fast_clear_op; + dw4 |= fast_clear_op; BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); @@ -249,6 +246,25 @@ upload_ps_state(struct brw_context *brw) ADVANCE_BATCH(); } +static void +upload_ps_state(struct brw_context *brw) +{ + /* BRW_NEW_FS_PROG_DATA */ + const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; + const struct gl_context *ctx = &brw->ctx; + /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */ + const bool enable_dual_src_blend = prog_data->dual_src_blend && + (ctx->Color.BlendEnabled & 1) && + ctx->Color.Blend[0]._UsesDualSrc; + /* _NEW_BUFFERS, _NEW_MULTISAMPLE */ + const unsigned sample_mask = + brw->is_haswell ? gen6_determine_sample_mask(brw) : 0; + + gen7_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data, + enable_dual_src_blend, sample_mask, + brw->wm.fast_clear_op); +} + const struct brw_tracked_state gen7_ps_state = { .dirty = { .mesa = _NEW_BUFFERS | From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/gen8: Expose state base address setup Message-ID: <20150429215500.BD303761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: d7e49fba9a48b5f90c0ce8b7d0c0588545090a7f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7e49fba9a48b5f90c0ce8b7d0c0588545090a7f Author: Topi Pohjolainen Date: Mon Mar 2 11:29:05 2015 +0200 i965/gen8: Expose state base address setup Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 3 +++ src/mesa/drivers/dri/i965/gen8_misc_state.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 13d541b..a2127d1 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -171,6 +171,9 @@ void brw_upload_invariant_state(struct brw_context *brw); uint32_t brw_depthbuffer_format(struct brw_context *brw); +/* gen8_misc_state.c */ +void gen8_upload_state_base_address(struct brw_context *brw); + /*********************************************************************** * brw_state.c diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c index 88e425f..b20038e 100644 --- a/src/mesa/drivers/dri/i965/gen8_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c @@ -29,7 +29,7 @@ /** * Define the base addresses which some state is referenced from. */ -static void upload_state_base_address(struct brw_context *brw) +void gen8_upload_state_base_address(struct brw_context *brw) { uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; int pkt_len = brw->gen >= 9 ? 19 : 16; @@ -78,5 +78,5 @@ const struct brw_tracked_state gen8_state_base_address = { .brw = BRW_NEW_BATCH | BRW_NEW_PROGRAM_CACHE, }, - .emit = upload_state_base_address + .emit = gen8_upload_state_base_address }; From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/blorp: Refactor vertex buffer state setup Message-ID: <20150429215500.D24FF761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: bfdacac86cf82a1ae8d76e3282b8842f08a21c31 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfdacac86cf82a1ae8d76e3282b8842f08a21c31 Author: Topi Pohjolainen Date: Fri Feb 27 11:17:05 2015 +0200 i965/blorp: Refactor vertex buffer state setup Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 60 +++++++++++++++++------------- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index e45705a..6c139ec 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -93,6 +93,37 @@ gen6_blorp_emit_state_base_address(struct brw_context *brw, ADVANCE_BATCH(); } +static void +gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw, + unsigned num_elems, + unsigned vbo_size, + uint32_t vertex_offset) +{ + /* 3DSTATE_VERTEX_BUFFERS */ + const int num_buffers = 1; + const int batch_length = 1 + 4 * num_buffers; + + uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA | + (num_elems * sizeof(float)) << BRW_VB0_PITCH_SHIFT; + + if (brw->gen >= 7) + dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; + + if (brw->gen == 7) + dw0 |= GEN7_MOCS_L3 << 16; + + BEGIN_BATCH(batch_length); + OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2)); + OUT_BATCH(dw0); + /* start address */ + OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, + vertex_offset); + /* end address */ + OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, + vertex_offset + vbo_size - 1); + OUT_BATCH(0); + ADVANCE_BATCH(); +} void gen6_blorp_emit_vertices(struct brw_context *brw, @@ -144,32 +175,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw, memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE); } - /* 3DSTATE_VERTEX_BUFFERS */ - { - const int num_buffers = 1; - const int batch_length = 1 + 4 * num_buffers; - - uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA | - (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT; - - if (brw->gen >= 7) - dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; - - if (brw->gen == 7) - dw0 |= GEN7_MOCS_L3 << 16; - - BEGIN_BATCH(batch_length); - OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2)); - OUT_BATCH(dw0); - /* start address */ - OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, - vertex_offset); - /* end address */ - OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, - vertex_offset + GEN6_BLORP_VBO_SIZE - 1); - OUT_BATCH(0); - ADVANCE_BATCH(); - } + gen6_blorp_emit_vertex_buffer_state(brw, GEN6_BLORP_NUM_VUE_ELEMS, + GEN6_BLORP_VBO_SIZE, + vertex_offset); /* 3DSTATE_VERTEX_ELEMENTS * From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:00 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:00 -0700 (PDT) Subject: Mesa (master): i965/blorp: Remove unused arguments Message-ID: <20150429215500.F3683761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 25ce6c6943576e22d8d00049578d0e6cc5feea07 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=25ce6c6943576e22d8d00049578d0e6cc5feea07 Author: Topi Pohjolainen Date: Fri Jan 30 11:37:54 2015 +0200 i965/blorp: Remove unused arguments Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 7 ++----- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 20 +++++++------------- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 +++--- 3 files changed, 12 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 6aaae65..f277dee 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -380,8 +380,7 @@ gen6_blorp_emit_blend_state(struct brw_context *brw, const brw_blorp_params *params); uint32_t -gen6_blorp_emit_cc_state(struct brw_context *brw, - const brw_blorp_params *params); +gen6_blorp_emit_cc_state(struct brw_context *brw); uint32_t gen6_blorp_emit_wm_constants(struct brw_context *brw, @@ -393,7 +392,6 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw, uint32_t gen6_blorp_emit_binding_table(struct brw_context *brw, - const brw_blorp_params *params, uint32_t wm_surf_offset_renderbuffer, uint32_t wm_surf_offset_texture); @@ -406,8 +404,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw, const brw_blorp_params *params); void -gen6_blorp_emit_clip_disable(struct brw_context *brw, - const brw_blorp_params *params); +gen6_blorp_emit_clip_disable(struct brw_context *brw); void gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 14e073b..2fe2840 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -268,8 +268,7 @@ gen6_blorp_emit_blend_state(struct brw_context *brw, /* CC_STATE */ uint32_t -gen6_blorp_emit_cc_state(struct brw_context *brw, - const brw_blorp_params *params) +gen6_blorp_emit_cc_state(struct brw_context *brw) { uint32_t cc_state_offset; @@ -431,7 +430,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, /* BINDING_TABLE. See brw_wm_binding_table(). */ uint32_t gen6_blorp_emit_binding_table(struct brw_context *brw, - const brw_blorp_params *params, uint32_t wm_surf_offset_renderbuffer, uint32_t wm_surf_offset_texture) { @@ -502,7 +500,6 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw, */ static void gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw, - const brw_blorp_params *params, uint32_t sampler_offset) { BEGIN_BATCH(4); @@ -602,8 +599,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw, * output, but does spare a few electrons. */ void -gen6_blorp_emit_clip_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen6_blorp_emit_clip_disable(struct brw_context *brw) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2)); @@ -767,7 +763,6 @@ gen6_blorp_emit_constant_ps_disable(struct brw_context *brw, */ static void gen6_blorp_emit_binding_table_pointers(struct brw_context *brw, - const brw_blorp_params *params, uint32_t wm_bind_bo_offset) { BEGIN_BATCH(4); @@ -1036,7 +1031,7 @@ gen6_blorp_exec(struct brw_context *brw, gen6_blorp_emit_urb_config(brw, params); if (params->use_wm_prog) { cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); - cc_state_offset = gen6_blorp_emit_cc_state(brw, params); + cc_state_offset = gen6_blorp_emit_cc_state(brw); } depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params); gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset, @@ -1057,17 +1052,16 @@ gen6_blorp_exec(struct brw_context *brw, I915_GEM_DOMAIN_SAMPLER, 0); } wm_bind_bo_offset = - gen6_blorp_emit_binding_table(brw, params, + gen6_blorp_emit_binding_table(brw, wm_surf_offset_renderbuffer, wm_surf_offset_texture); sampler_offset = gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true); - - gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset); + gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset); } gen6_blorp_emit_vs_disable(brw, params); gen6_blorp_emit_gs_disable(brw, params); - gen6_blorp_emit_clip_disable(brw, params); + gen6_blorp_emit_clip_disable(brw); gen6_blorp_emit_sf_config(brw, params); if (params->use_wm_prog) gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset); @@ -1075,7 +1069,7 @@ gen6_blorp_exec(struct brw_context *brw, gen6_blorp_emit_constant_ps_disable(brw, params); gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data); if (params->use_wm_prog) - gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset); + gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset); gen6_blorp_emit_viewport_state(brw, params); if (params->depth.mt) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index c9e7cb7..12f515d 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -786,7 +786,7 @@ gen7_blorp_exec(struct brw_context *brw, gen7_blorp_emit_urb_config(brw); if (params->use_wm_prog) { cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); - cc_state_offset = gen6_blorp_emit_cc_state(brw, params); + cc_state_offset = gen6_blorp_emit_cc_state(brw); gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset); gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset); } @@ -809,7 +809,7 @@ gen7_blorp_exec(struct brw_context *brw, false /* is_render_target */); } wm_bind_bo_offset = - gen6_blorp_emit_binding_table(brw, params, + gen6_blorp_emit_binding_table(brw, wm_surf_offset_renderbuffer, wm_surf_offset_texture); sampler_offset = @@ -821,7 +821,7 @@ gen7_blorp_exec(struct brw_context *brw, gen7_blorp_emit_ds_disable(brw); gen7_blorp_emit_gs_disable(brw); gen7_blorp_emit_streamout_disable(brw); - gen6_blorp_emit_clip_disable(brw, params); + gen6_blorp_emit_clip_disable(brw); gen7_blorp_emit_sf_config(brw, params); gen7_blorp_emit_wm_config(brw, params, prog_data); if (params->use_wm_prog) { From tpohjola at kemper.freedesktop.org Wed Apr 29 21:55:01 2015 From: tpohjola at kemper.freedesktop.org (Topi Pohjolainen) Date: Wed, 29 Apr 2015 14:55:01 -0700 (PDT) Subject: Mesa (master): i965/blorp: Add support for layered rendering Message-ID: <20150429215501.2202F761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: dfd896699d9f640518c0fbafb0352f454d5fc466 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfd896699d9f640518c0fbafb0352f454d5fc466 Author: Topi Pohjolainen Date: Fri Mar 27 16:25:56 2015 +0200 i965/blorp: Add support for layered rendering Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 6 ++++-- src/mesa/drivers/dri/i965/brw_blorp.h | 4 +++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 2 +- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 8f82851..b404869 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -156,7 +156,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, brw_blorp_params::brw_blorp_params(unsigned num_varyings, - unsigned num_draw_buffers) + unsigned num_draw_buffers, + unsigned num_layers) : x0(0), y0(0), x1(0), @@ -165,7 +166,8 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings, hiz_op(GEN6_HIZ_OP_NONE), use_wm_prog(false), num_varyings(num_varyings), - num_draw_buffers(num_draw_buffers) + num_draw_buffers(num_draw_buffers), + num_layers(num_layers) { } diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index c9957a6..dd28d81 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -212,7 +212,8 @@ class brw_blorp_params { public: brw_blorp_params(unsigned num_varyings = 0, - unsigned num_draw_buffers = 1); + unsigned num_draw_buffers = 1, + unsigned num_layers = 1); virtual uint32_t get_wm_prog(struct brw_context *brw, brw_blorp_prog_data **prog_data) const = 0; @@ -230,6 +231,7 @@ public: brw_blorp_wm_push_constants wm_push_consts; const unsigned num_varyings; const unsigned num_draw_buffers; + const unsigned num_layers; }; diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index bfd2001..ed08898 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -992,7 +992,7 @@ gen6_blorp_emit_primitive(struct brw_context *brw, GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL); OUT_BATCH(3); /* vertex count per instance */ OUT_BATCH(0); - OUT_BATCH(1); /* instance count */ + OUT_BATCH(params->num_layers); /* instance count */ OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 3065a4c..2bdc82b 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -753,7 +753,7 @@ gen7_blorp_emit_primitive(struct brw_context *brw, _3DPRIM_RECTLIST); OUT_BATCH(3); /* vertex count per instance */ OUT_BATCH(0); - OUT_BATCH(1); /* instance count */ + OUT_BATCH(params->num_layers); /* instance count */ OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); From imirkin at kemper.freedesktop.org Wed Apr 29 22:04:16 2015 From: imirkin at kemper.freedesktop.org (Ilia Mirkin) Date: Wed, 29 Apr 2015 15:04:16 -0700 (PDT) Subject: Mesa (master): gk110/ir: fix set with a register dest to not auto-set the abs flag Message-ID: <20150429220416.7C99C761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 515ac907e68ae1485bd9c65d7351dfb3c3d1e33f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=515ac907e68ae1485bd9c65d7351dfb3c3d1e33f Author: Ilia Mirkin Date: Wed Apr 29 18:01:53 2015 -0400 gk110/ir: fix set with a register dest to not auto-set the abs flag This was causing src0 to always have the absolute value flag set. Signed-off-by: Ilia Mirkin Cc: mesa-stable at lists.freedesktop.org --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index a73bee2..d7c6b80 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp @@ -971,7 +971,7 @@ CodeEmitterGK110::emitSET(const CmpInstruction *i) code[0] |= 0x1c; } else { switch (i->sType) { - case TYPE_F32: op2 = 0x000; op1 = 0x820; break; + case TYPE_F32: op2 = 0x000; op1 = 0x800; break; case TYPE_F64: op2 = 0x080; op1 = 0x900; break; default: op2 = 0x1a8; From imirkin at kemper.freedesktop.org Thu Apr 30 03:35:42 2015 From: imirkin at kemper.freedesktop.org (Ilia Mirkin) Date: Wed, 29 Apr 2015 20:35:42 -0700 (PDT) Subject: Mesa (master): nv50/ir: fix asFlow() const helper for OP_JOIN Message-ID: <20150430033542.48A80761EA@kemper.freedesktop.org> Module: Mesa Branch: master Commit: db269ae495425849804fb1d05cfe42b0d3d304b3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db269ae495425849804fb1d05cfe42b0d3d304b3 Author: Ilia Mirkin Date: Wed Apr 29 23:33:27 2015 -0400 nv50/ir: fix asFlow() const helper for OP_JOIN Signed-off-by: Ilia Mirkin Cc: mesa-stable at lists.freedesktop.org --- src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h index 255324f..e465f24 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h @@ -302,7 +302,7 @@ FlowInstruction *Instruction::asFlow() const FlowInstruction *Instruction::asFlow() const { - if (op >= OP_BRA && op <= OP_JOINAT) + if (op >= OP_BRA && op <= OP_JOIN) return static_cast(this); return NULL; } From imirkin at kemper.freedesktop.org Thu Apr 30 03:35:42 2015 From: imirkin at kemper.freedesktop.org (Ilia Mirkin) Date: Wed, 29 Apr 2015 20:35:42 -0700 (PDT) Subject: Mesa (master): nvc0/ir: fix predicated PFETCH emission Message-ID: <20150430033542.41886761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: a9d08a250ada5fbd4e3f78f8e4119ec295d692cf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9d08a250ada5fbd4e3f78f8e4119ec295d692cf Author: Ilia Mirkin Date: Wed Apr 29 23:05:44 2015 -0400 nvc0/ir: fix predicated PFETCH emission src1 would contain the predicate, which would get emitted as a register source by an undiscerning srcId helper. Work around this in the same way as in emitTEX. Signed-off-by: Ilia Mirkin Cc: mesa-stable at lists.freedesktop.org --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 4 +++- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index d7c6b80..a6e6c1f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp @@ -1333,8 +1333,10 @@ CodeEmitterGK110::emitPFETCH(const Instruction *i) emitPredicate(i); + const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) + defId(i->def(0), 2); - srcId(i->src(1), 10); + srcId(i, 1, 10); } void diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index 1a4f6e0..4ad098e 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp @@ -1495,8 +1495,10 @@ CodeEmitterNVC0::emitPFETCH(const Instruction *i) emitPredicate(i); + const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) + defId(i->def(0), 14); - srcId(i->src(1), 20); + srcId(i, 1, 20); } void From imirkin at kemper.freedesktop.org Thu Apr 30 06:03:57 2015 From: imirkin at kemper.freedesktop.org (Ilia Mirkin) Date: Wed, 29 Apr 2015 23:03:57 -0700 (PDT) Subject: Mesa (master): nvc0/ir: fix predicated PFETCH for real Message-ID: <20150430060357.B3897761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 33f0d1138d6ffa4596d3deda68fa5ba9a3d7cf86 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33f0d1138d6ffa4596d3deda68fa5ba9a3d7cf86 Author: Ilia Mirkin Date: Thu Apr 30 02:01:22 2015 -0400 nvc0/ir: fix predicated PFETCH for real Commit a9d08a250 accidentally didn't make use of the new src1 variable. Use it. Signed-off-by: Ilia Mirkin Cc: mesa-stable at lists.freedesktop.org --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index a6e6c1f..6bb9620 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp @@ -1336,7 +1336,7 @@ CodeEmitterGK110::emitPFETCH(const Instruction *i) const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) defId(i->def(0), 2); - srcId(i, 1, 10); + srcId(i, src1, 10); } void diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index 4ad098e..d9aed34 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp @@ -1498,7 +1498,7 @@ CodeEmitterNVC0::emitPFETCH(const Instruction *i) const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) defId(i->def(0), 14); - srcId(i, 1, 20); + srcId(i, src1, 20); } void From mareko at kemper.freedesktop.org Thu Apr 30 12:43:15 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:15 -0700 (PDT) Subject: Mesa (master): dri_interface: add an interface for fences Message-ID: <20150430124315.A2035761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: b02a5bf3ba04608d50916a4ca00261461280d548 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b02a5bf3ba04608d50916a4ca00261461280d548 Author: Marek Ol??k Date: Fri Apr 10 10:43:26 2015 +0200 dri_interface: add an interface for fences --- include/GL/internal/dri_interface.h | 60 +++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h index eb7da23..c827bb6 100644 --- a/include/GL/internal/dri_interface.h +++ b/include/GL/internal/dri_interface.h @@ -85,6 +85,7 @@ typedef struct __DRIdri2ExtensionRec __DRIdri2Extension; typedef struct __DRIdri2LoaderExtensionRec __DRIdri2LoaderExtension; typedef struct __DRI2flushExtensionRec __DRI2flushExtension; typedef struct __DRI2throttleExtensionRec __DRI2throttleExtension; +typedef struct __DRI2fenceExtensionRec __DRI2fenceExtension; typedef struct __DRIimageLoaderExtensionRec __DRIimageLoaderExtension; @@ -339,6 +340,65 @@ struct __DRI2throttleExtensionRec { enum __DRI2throttleReason reason); }; + +/** + * Extension for fences / synchronization objects. + */ + +#define __DRI2_FENCE "DRI2_Fence" +#define __DRI2_FENCE_VERSION 1 + +#define __DRI2_FENCE_TIMEOUT_INFINITE 0xffffffffffffffffllu + +#define __DRI2_FENCE_FLAG_FLUSH_COMMANDS (1 << 0) + +struct __DRI2fenceExtensionRec { + __DRIextension base; + + /** + * Create and insert a fence into the command stream of the context. + */ + void *(*create_fence)(__DRIcontext *ctx); + + /** + * Get a fence associated with the OpenCL event object. + * This can be NULL, meaning that OpenCL interoperability is not supported. + */ + void *(*get_fence_from_cl_event)(__DRIscreen *screen, intptr_t cl_event); + + /** + * Destroy a fence. + */ + void (*destroy_fence)(__DRIscreen *screen, void *fence); + + /** + * This function waits and doesn't return until the fence is signalled + * or the timeout expires. It returns true if the fence has been signaled. + * + * \param ctx the context where commands are flushed + * \param fence the fence + * \param flags a combination of __DRI2_FENCE_FLAG_xxx flags + * \param timeout the timeout in ns or __DRI2_FENCE_TIMEOUT_INFINITE + */ + GLboolean (*client_wait_sync)(__DRIcontext *ctx, void *fence, + unsigned flags, uint64_t timeout); + + /** + * This function enqueues a wait command into the command stream of + * the context and then returns. When the execution reaches the wait + * command, no further execution will be done in the context until + * the fence is signaled. This is a no-op if the device doesn't support + * parallel execution of contexts. + * + * \param ctx the context where the waiting is done + * \param fence the fence + * \param flags a combination of __DRI2_FENCE_FLAG_xxx flags that make + * sense with this function (right now there are none) + */ + void (*server_wait_sync)(__DRIcontext *ctx, void *fence, unsigned flags); +}; + + /*@}*/ /** From mareko at kemper.freedesktop.org Thu Apr 30 12:43:15 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:15 -0700 (PDT) Subject: Mesa (master): mesa: add GL_OES_EGL_sync Message-ID: <20150430124315.AC716761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 592ee249a139a46168cd8e3335039ce28e8a2c39 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=592ee249a139a46168cd8e3335039ce28e8a2c39 Author: Marek Ol??k Date: Thu Apr 9 23:26:14 2015 +0200 mesa: add GL_OES_EGL_sync This is an empty extension whose presence means that EGL sync objects can be used with ES contexts. --- src/mesa/main/extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c index 3d4965c..9be8993 100644 --- a/src/mesa/main/extensions.c +++ b/src/mesa/main/extensions.c @@ -298,6 +298,7 @@ static const struct extension extension_table[] = { { "GL_OES_depth_texture", o(ARB_depth_texture), ES2, 2006 }, { "GL_OES_depth_texture_cube_map", o(OES_depth_texture_cube_map), ES2, 2012 }, { "GL_OES_draw_texture", o(OES_draw_texture), ES1, 2004 }, + { "GL_OES_EGL_sync", o(dummy_true), ES1 | ES2, 2010 }, /* FIXME: Mesa expects GL_OES_EGL_image to be available in OpenGL contexts. */ { "GL_OES_EGL_image", o(OES_EGL_image), GL | ES1 | ES2, 2006 }, { "GL_OES_EGL_image_external", o(OES_EGL_image_external), ES1 | ES2, 2010 }, From mareko at kemper.freedesktop.org Thu Apr 30 12:43:15 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:15 -0700 (PDT) Subject: Mesa (master): egl/dri2: implement EGL_KHR_fence_sync Message-ID: <20150430124315.BA2EA761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 9a0bda2430f10fbf43c64573412d97b6cc38e5d7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a0bda2430f10fbf43c64573412d97b6cc38e5d7 Author: Marek Ol??k Date: Fri Apr 10 10:56:02 2015 +0200 egl/dri2: implement EGL_KHR_fence_sync --- src/egl/drivers/dri2/egl_dri2.c | 95 +++++++++++++++++++++++++++++++++++++++ src/egl/drivers/dri2/egl_dri2.h | 9 ++++ src/egl/main/eglapi.c | 34 +++++++++++--- 3 files changed, 133 insertions(+), 5 deletions(-) diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index 14b9be9..97175ae 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -51,6 +51,7 @@ #endif #include "egl_dri2.h" +#include "../util/u_atomic.h" const __DRIuseInvalidateExtension use_invalidate = { .base = { __DRI_USE_INVALIDATE, 1 } @@ -527,6 +528,10 @@ dri2_setup_screen(_EGLDisplay *disp) disp->Extensions.EXT_create_context_robustness = EGL_TRUE; } + if (dri2_dpy->fence) { + disp->Extensions.KHR_fence_sync = EGL_TRUE; + } + if (dri2_dpy->image) { if (dri2_dpy->image->base.version >= 10 && dri2_dpy->image->getCapabilities != NULL) { @@ -620,6 +625,9 @@ dri2_create_screen(_EGLDisplay *disp) if (strcmp(extensions[i]->name, __DRI2_CONFIG_QUERY) == 0) { dri2_dpy->config = (__DRI2configQueryExtension *) extensions[i]; } + if (strcmp(extensions[i]->name, __DRI2_FENCE) == 0) { + dri2_dpy->fence = (__DRI2fenceExtension *) extensions[i]; + } } } else { assert(dri2_dpy->swrast); @@ -2181,6 +2189,90 @@ dri2_query_wayland_buffer_wl(_EGLDriver *drv, _EGLDisplay *disp, #endif static void +dri2_egl_ref_sync(struct dri2_egl_sync *sync) +{ + p_atomic_inc(&sync->refcount); +} + +static void +dri2_egl_unref_sync(struct dri2_egl_display *dri2_dpy, + struct dri2_egl_sync *dri2_sync) +{ + if (p_atomic_dec_zero(&dri2_sync->refcount)) { + dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, dri2_sync->fence); + free(dri2_sync); + } +} + +static _EGLSync * +dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy, + EGLenum type, const EGLint *attrib_list) +{ + _EGLContext *ctx = _eglGetCurrentContext(); + struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy); + struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx); + struct dri2_egl_sync *dri2_sync; + + dri2_sync = calloc(1, sizeof(struct dri2_egl_sync)); + if (!dri2_sync) { + _eglError(EGL_BAD_ALLOC, "eglCreateSyncKHR"); + return NULL; + } + + if (!_eglInitSync(&dri2_sync->base, dpy, type, attrib_list)) { + free(dri2_sync); + return NULL; + } + + switch (type) { + case EGL_SYNC_FENCE_KHR: + dri2_sync->fence = dri2_dpy->fence->create_fence(dri2_ctx->dri_context); + break; + } + + p_atomic_set(&dri2_sync->refcount, 1); + return &dri2_sync->base; +} + +static EGLBoolean +dri2_destroy_sync(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync) +{ + struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy); + struct dri2_egl_sync *dri2_sync = dri2_egl_sync(sync); + + dri2_egl_unref_sync(dri2_dpy, dri2_sync); + return EGL_TRUE; +} + +static EGLint +dri2_client_wait_sync(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, + EGLint flags, EGLTimeKHR timeout) +{ + _EGLContext *ctx = _eglGetCurrentContext(); + struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy); + struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx); + struct dri2_egl_sync *dri2_sync = dri2_egl_sync(sync); + unsigned wait_flags = 0; + EGLint ret = EGL_CONDITION_SATISFIED_KHR; + + if (flags & EGL_SYNC_FLUSH_COMMANDS_BIT_KHR) + wait_flags |= __DRI2_FENCE_FLAG_FLUSH_COMMANDS; + + /* the sync object should take a reference while waiting */ + dri2_egl_ref_sync(dri2_sync); + + if (dri2_dpy->fence->client_wait_sync(dri2_ctx->dri_context, + dri2_sync->fence, wait_flags, + timeout)) + dri2_sync->base.SyncStatus = EGL_SIGNALED_KHR; + else + ret = EGL_TIMEOUT_EXPIRED_KHR; + + dri2_egl_unref_sync(dri2_dpy, dri2_sync); + return ret; +} + +static void dri2_unload(_EGLDriver *drv) { struct dri2_egl_driver *dri2_drv = dri2_egl_driver(drv); @@ -2292,6 +2384,9 @@ _eglBuiltInDriverDRI2(const char *args) dri2_drv->base.API.QueryWaylandBufferWL = dri2_query_wayland_buffer_wl; #endif dri2_drv->base.API.GetSyncValuesCHROMIUM = dri2_get_sync_values_chromium; + dri2_drv->base.API.CreateSyncKHR = dri2_create_sync; + dri2_drv->base.API.ClientWaitSyncKHR = dri2_client_wait_sync; + dri2_drv->base.API.DestroySyncKHR = dri2_destroy_sync; dri2_drv->base.Name = "DRI2"; dri2_drv->base.Unload = dri2_unload; diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h index 167b3b1..371fb4a 100644 --- a/src/egl/drivers/dri2/egl_dri2.h +++ b/src/egl/drivers/dri2/egl_dri2.h @@ -74,6 +74,7 @@ #include "egllog.h" #include "eglsurface.h" #include "eglimage.h" +#include "eglsync.h" #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -164,6 +165,7 @@ struct dri2_egl_display const __DRIimageExtension *image; const __DRIrobustnessExtension *robustness; const __DRI2configQueryExtension *config; + const __DRI2fenceExtension *fence; int fd; int own_device; @@ -283,6 +285,12 @@ struct dri2_egl_image __DRIimage *dri_image; }; +struct dri2_egl_sync { + _EGLSync base; + int refcount; + void *fence; +}; + /* From xmlpool/options.h, user exposed so should be stable */ #define DRI_CONF_VBLANK_NEVER 0 #define DRI_CONF_VBLANK_DEF_INTERVAL_0 1 @@ -292,6 +300,7 @@ struct dri2_egl_image /* standard typecasts */ _EGL_DRIVER_STANDARD_TYPECASTS(dri2_egl) _EGL_DRIVER_TYPECAST(dri2_egl_image, _EGLImage, obj) +_EGL_DRIVER_TYPECAST(dri2_egl_sync, _EGLSync, obj) extern const __DRIimageLookupExtension image_lookup_extension; extern const __DRIuseInvalidateExtension use_invalidate; diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c index 8b7b9be..dd972b2 100644 --- a/src/egl/main/eglapi.c +++ b/src/egl/main/eglapi.c @@ -1657,13 +1657,30 @@ EGLSyncKHR EGLAPIENTRY eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list) { _EGLDisplay *disp = _eglLockDisplay(dpy); + _EGLContext *ctx = _eglGetCurrentContext(); _EGLDriver *drv; _EGLSync *sync; EGLSyncKHR ret; _EGL_CHECK_DISPLAY(disp, EGL_NO_SYNC_KHR, drv); - if (!disp->Extensions.KHR_reusable_sync) - RETURN_EGL_EVAL(disp, EGL_NO_SYNC_KHR); + + /* return an error if the client API doesn't support GL_OES_EGL_sync */ + if (!ctx || ctx->Resource.Display != dpy || + ctx->ClientAPI != EGL_OPENGL_ES_API) + RETURN_EGL_ERROR(disp, EGL_BAD_MATCH, EGL_NO_SYNC_KHR); + + switch (type) { + case EGL_SYNC_FENCE_KHR: + if (!disp->Extensions.KHR_fence_sync) + RETURN_EGL_ERROR(disp, EGL_BAD_ATTRIBUTE, EGL_NO_SYNC_KHR); + break; + case EGL_SYNC_REUSABLE_KHR: + if (!disp->Extensions.KHR_reusable_sync) + RETURN_EGL_ERROR(disp, EGL_BAD_ATTRIBUTE, EGL_NO_SYNC_KHR); + break; + default: + RETURN_EGL_ERROR(disp, EGL_BAD_ATTRIBUTE, EGL_NO_SYNC_KHR); + } sync = drv->API.CreateSyncKHR(drv, disp, type, attrib_list); ret = (sync) ? _eglLinkSync(sync) : EGL_NO_SYNC_KHR; @@ -1681,7 +1698,8 @@ eglDestroySyncKHR(EGLDisplay dpy, EGLSyncKHR sync) EGLBoolean ret; _EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv); - assert(disp->Extensions.KHR_reusable_sync); + assert(disp->Extensions.KHR_reusable_sync || + disp->Extensions.KHR_fence_sync); _eglUnlinkSync(s); ret = drv->API.DestroySyncKHR(drv, disp, s); @@ -1699,7 +1717,12 @@ eglClientWaitSyncKHR(EGLDisplay dpy, EGLSyncKHR sync, EGLint flags, EGLTimeKHR t EGLint ret; _EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv); - assert(disp->Extensions.KHR_reusable_sync); + assert(disp->Extensions.KHR_reusable_sync || + disp->Extensions.KHR_fence_sync); + + if (s->SyncStatus == EGL_SIGNALED_KHR) + RETURN_EGL_EVAL(disp, EGL_CONDITION_SATISFIED_KHR); + ret = drv->API.ClientWaitSyncKHR(drv, disp, s, flags, timeout); RETURN_EGL_EVAL(disp, ret); @@ -1731,7 +1754,8 @@ eglGetSyncAttribKHR(EGLDisplay dpy, EGLSyncKHR sync, EGLint attribute, EGLint *v EGLBoolean ret; _EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv); - assert(disp->Extensions.KHR_reusable_sync); + assert(disp->Extensions.KHR_reusable_sync || + disp->Extensions.KHR_fence_sync); ret = drv->API.GetSyncAttribKHR(drv, disp, s, attribute, value); RETURN_EGL_EVAL(disp, ret); From mareko at kemper.freedesktop.org Thu Apr 30 12:43:15 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:15 -0700 (PDT) Subject: Mesa (master): egl/dri2: implement EGL_KHR_wait_sync Message-ID: <20150430124315.C6D72761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: a8617cc0428dcc8340cb85776e122c6534a0fa11 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8617cc0428dcc8340cb85776e122c6534a0fa11 Author: Marek Ol??k Date: Fri Apr 10 12:04:18 2015 +0200 egl/dri2: implement EGL_KHR_wait_sync --- src/egl/drivers/dri2/egl_dri2.c | 15 +++++++++++++++ src/egl/main/eglapi.c | 28 ++++++++++++++++++++++++++++ src/egl/main/eglapi.h | 2 ++ src/egl/main/egldisplay.h | 1 + src/egl/main/eglfallbacks.c | 1 + 5 files changed, 47 insertions(+) diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index 97175ae..e096a7d 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -530,6 +530,7 @@ dri2_setup_screen(_EGLDisplay *disp) if (dri2_dpy->fence) { disp->Extensions.KHR_fence_sync = EGL_TRUE; + disp->Extensions.KHR_wait_sync = EGL_TRUE; } if (dri2_dpy->image) { @@ -2272,6 +2273,19 @@ dri2_client_wait_sync(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, return ret; } +static EGLint +dri2_server_wait_sync(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync) +{ + _EGLContext *ctx = _eglGetCurrentContext(); + struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy); + struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx); + struct dri2_egl_sync *dri2_sync = dri2_egl_sync(sync); + + dri2_dpy->fence->server_wait_sync(dri2_ctx->dri_context, + dri2_sync->fence, 0); + return EGL_TRUE; +} + static void dri2_unload(_EGLDriver *drv) { @@ -2386,6 +2400,7 @@ _eglBuiltInDriverDRI2(const char *args) dri2_drv->base.API.GetSyncValuesCHROMIUM = dri2_get_sync_values_chromium; dri2_drv->base.API.CreateSyncKHR = dri2_create_sync; dri2_drv->base.API.ClientWaitSyncKHR = dri2_client_wait_sync; + dri2_drv->base.API.WaitSyncKHR = dri2_server_wait_sync; dri2_drv->base.API.DestroySyncKHR = dri2_destroy_sync; dri2_drv->base.Name = "DRI2"; diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c index dd972b2..65a730a 100644 --- a/src/egl/main/eglapi.c +++ b/src/egl/main/eglapi.c @@ -406,6 +406,7 @@ _eglCreateExtensionsString(_EGLDisplay *dpy) _EGL_CHECK_EXTENSION(KHR_reusable_sync); _EGL_CHECK_EXTENSION(KHR_fence_sync); + _EGL_CHECK_EXTENSION(KHR_wait_sync); _EGL_CHECK_EXTENSION(KHR_surfaceless_context); _EGL_CHECK_EXTENSION(KHR_create_context); @@ -1216,6 +1217,7 @@ eglGetProcAddress(const char *procname) { "eglCreateSyncKHR", (_EGLProc) eglCreateSyncKHR }, { "eglDestroySyncKHR", (_EGLProc) eglDestroySyncKHR }, { "eglClientWaitSyncKHR", (_EGLProc) eglClientWaitSyncKHR }, + { "eglWaitSyncKHR", (_EGLProc) eglWaitSyncKHR }, { "eglSignalSyncKHR", (_EGLProc) eglSignalSyncKHR }, { "eglGetSyncAttribKHR", (_EGLProc) eglGetSyncAttribKHR }, #ifdef EGL_NOK_swap_region @@ -1729,6 +1731,32 @@ eglClientWaitSyncKHR(EGLDisplay dpy, EGLSyncKHR sync, EGLint flags, EGLTimeKHR t } +EGLint EGLAPIENTRY +eglWaitSyncKHR(EGLDisplay dpy, EGLSyncKHR sync, EGLint flags) +{ + _EGLDisplay *disp = _eglLockDisplay(dpy); + _EGLSync *s = _eglLookupSync(sync, disp); + _EGLContext *ctx = _eglGetCurrentContext(); + _EGLDriver *drv; + EGLint ret; + + _EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv); + assert(disp->Extensions.KHR_wait_sync); + + /* return an error if the client API doesn't support GL_OES_EGL_sync */ + if (ctx == EGL_NO_CONTEXT || ctx->ClientAPI != EGL_OPENGL_ES_API) + RETURN_EGL_ERROR(disp, EGL_BAD_MATCH, EGL_FALSE); + + /* the API doesn't allow any flags yet */ + if (flags != 0) + RETURN_EGL_ERROR(disp, EGL_BAD_PARAMETER, EGL_FALSE); + + ret = drv->API.WaitSyncKHR(drv, disp, s); + + RETURN_EGL_EVAL(disp, ret); +} + + EGLBoolean EGLAPIENTRY eglSignalSyncKHR(EGLDisplay dpy, EGLSyncKHR sync, EGLenum mode) { diff --git a/src/egl/main/eglapi.h b/src/egl/main/eglapi.h index 3245327..7462b35 100644 --- a/src/egl/main/eglapi.h +++ b/src/egl/main/eglapi.h @@ -105,6 +105,7 @@ typedef EGLBoolean (*DestroyImageKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLI typedef _EGLSync *(*CreateSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, EGLenum type, const EGLint *attrib_list); typedef EGLBoolean (*DestroySyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync); typedef EGLint (*ClientWaitSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, EGLint flags, EGLTimeKHR timeout); +typedef EGLint (*WaitSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync); typedef EGLBoolean (*SignalSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, EGLenum mode); typedef EGLBoolean (*GetSyncAttribKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, EGLint attribute, EGLint *value); @@ -201,6 +202,7 @@ struct _egl_api CreateSyncKHR_t CreateSyncKHR; DestroySyncKHR_t DestroySyncKHR; ClientWaitSyncKHR_t ClientWaitSyncKHR; + WaitSyncKHR_t WaitSyncKHR; SignalSyncKHR_t SignalSyncKHR; GetSyncAttribKHR_t GetSyncAttribKHR; diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h index 4a1fb4a..70381bc 100644 --- a/src/egl/main/egldisplay.h +++ b/src/egl/main/egldisplay.h @@ -106,6 +106,7 @@ struct _egl_extensions EGLBoolean KHR_reusable_sync; EGLBoolean KHR_fence_sync; + EGLBoolean KHR_wait_sync; EGLBoolean KHR_surfaceless_context; EGLBoolean KHR_create_context; diff --git a/src/egl/main/eglfallbacks.c b/src/egl/main/eglfallbacks.c index c108ca7..83d7756 100644 --- a/src/egl/main/eglfallbacks.c +++ b/src/egl/main/eglfallbacks.c @@ -107,6 +107,7 @@ _eglInitDriverFallbacks(_EGLDriver *drv) drv->API.CreateSyncKHR = NULL; drv->API.DestroySyncKHR = NULL; drv->API.ClientWaitSyncKHR = NULL; + drv->API.WaitSyncKHR = NULL; drv->API.SignalSyncKHR = NULL; drv->API.GetSyncAttribKHR = _eglGetSyncAttribKHR; From mareko at kemper.freedesktop.org Thu Apr 30 12:43:15 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:15 -0700 (PDT) Subject: Mesa (master): egl/dri2: implement EGL_KHR_cl_event2 (v2) Message-ID: <20150430124315.D3E3E761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 290a3eb7507f7f2949753a77c425ed2bb6fd0dd1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=290a3eb7507f7f2949753a77c425ed2bb6fd0dd1 Author: Marek Ol??k Date: Fri Apr 10 13:16:30 2015 +0200 egl/dri2: implement EGL_KHR_cl_event2 (v2) v2: fix the SYNC_CONDITION query --- src/egl/drivers/dri2/egl_dri2.c | 25 ++++++++++++++-- src/egl/main/eglapi.c | 30 +++++++++++++++++-- src/egl/main/eglapi.h | 2 +- src/egl/main/egldisplay.h | 1 + src/egl/main/eglsync.c | 62 +++++++++++++++++++++++++++++++++++---- src/egl/main/eglsync.h | 3 +- 6 files changed, 111 insertions(+), 12 deletions(-) diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index e096a7d..34d6bfe 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -531,6 +531,8 @@ dri2_setup_screen(_EGLDisplay *disp) if (dri2_dpy->fence) { disp->Extensions.KHR_fence_sync = EGL_TRUE; disp->Extensions.KHR_wait_sync = EGL_TRUE; + if (dri2_dpy->fence->get_fence_from_cl_event) + disp->Extensions.KHR_cl_event2 = EGL_TRUE; } if (dri2_dpy->image) { @@ -2207,7 +2209,8 @@ dri2_egl_unref_sync(struct dri2_egl_display *dri2_dpy, static _EGLSync * dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy, - EGLenum type, const EGLint *attrib_list) + EGLenum type, const EGLint *attrib_list, + const EGLAttribKHR *attrib_list64) { _EGLContext *ctx = _eglGetCurrentContext(); struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy); @@ -2220,7 +2223,8 @@ dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy, return NULL; } - if (!_eglInitSync(&dri2_sync->base, dpy, type, attrib_list)) { + if (!_eglInitSync(&dri2_sync->base, dpy, type, attrib_list, + attrib_list64)) { free(dri2_sync); return NULL; } @@ -2229,6 +2233,23 @@ dri2_create_sync(_EGLDriver *drv, _EGLDisplay *dpy, case EGL_SYNC_FENCE_KHR: dri2_sync->fence = dri2_dpy->fence->create_fence(dri2_ctx->dri_context); break; + + case EGL_SYNC_CL_EVENT_KHR: + dri2_sync->fence = dri2_dpy->fence->get_fence_from_cl_event( + dri2_dpy->dri_screen, + dri2_sync->base.CLEvent); + /* this can only happen if the cl_event passed in is invalid. */ + if (!dri2_sync->fence) { + _eglError(EGL_BAD_ATTRIBUTE, "eglCreateSyncKHR"); + free(dri2_sync); + return NULL; + } + + /* the initial status must be "signaled" if the cl_event is signaled */ + if (dri2_dpy->fence->client_wait_sync(dri2_ctx->dri_context, + dri2_sync->fence, 0, 0)) + dri2_sync->base.SyncStatus = EGL_SIGNALED_KHR; + break; } p_atomic_set(&dri2_sync->refcount, 1); diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c index 65a730a..ec41aa3 100644 --- a/src/egl/main/eglapi.c +++ b/src/egl/main/eglapi.c @@ -407,6 +407,7 @@ _eglCreateExtensionsString(_EGLDisplay *dpy) _EGL_CHECK_EXTENSION(KHR_reusable_sync); _EGL_CHECK_EXTENSION(KHR_fence_sync); _EGL_CHECK_EXTENSION(KHR_wait_sync); + _EGL_CHECK_EXTENSION(KHR_cl_event2); _EGL_CHECK_EXTENSION(KHR_surfaceless_context); _EGL_CHECK_EXTENSION(KHR_create_context); @@ -1215,6 +1216,7 @@ eglGetProcAddress(const char *procname) { "eglCreateImageKHR", (_EGLProc) eglCreateImageKHR }, { "eglDestroyImageKHR", (_EGLProc) eglDestroyImageKHR }, { "eglCreateSyncKHR", (_EGLProc) eglCreateSyncKHR }, + { "eglCreateSync64KHR", (_EGLProc) eglCreateSync64KHR }, { "eglDestroySyncKHR", (_EGLProc) eglDestroySyncKHR }, { "eglClientWaitSyncKHR", (_EGLProc) eglClientWaitSyncKHR }, { "eglWaitSyncKHR", (_EGLProc) eglWaitSyncKHR }, @@ -1655,8 +1657,9 @@ eglDestroyImageKHR(EGLDisplay dpy, EGLImageKHR image) } -EGLSyncKHR EGLAPIENTRY -eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list) +static EGLSyncKHR +_eglCreateSync(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list, + const EGLAttribKHR *attrib_list64, EGLBoolean is64) { _EGLDisplay *disp = _eglLockDisplay(dpy); _EGLContext *ctx = _eglGetCurrentContext(); @@ -1666,6 +1669,9 @@ eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list) _EGL_CHECK_DISPLAY(disp, EGL_NO_SYNC_KHR, drv); + if (!disp->Extensions.KHR_cl_event2 && is64) + RETURN_EGL_EVAL(disp, EGL_NO_SYNC_KHR); + /* return an error if the client API doesn't support GL_OES_EGL_sync */ if (!ctx || ctx->Resource.Display != dpy || ctx->ClientAPI != EGL_OPENGL_ES_API) @@ -1680,17 +1686,35 @@ eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list) if (!disp->Extensions.KHR_reusable_sync) RETURN_EGL_ERROR(disp, EGL_BAD_ATTRIBUTE, EGL_NO_SYNC_KHR); break; + case EGL_SYNC_CL_EVENT_KHR: + if (!disp->Extensions.KHR_cl_event2) + RETURN_EGL_ERROR(disp, EGL_BAD_ATTRIBUTE, EGL_NO_SYNC_KHR); + break; default: RETURN_EGL_ERROR(disp, EGL_BAD_ATTRIBUTE, EGL_NO_SYNC_KHR); } - sync = drv->API.CreateSyncKHR(drv, disp, type, attrib_list); + sync = drv->API.CreateSyncKHR(drv, disp, type, attrib_list, attrib_list64); ret = (sync) ? _eglLinkSync(sync) : EGL_NO_SYNC_KHR; RETURN_EGL_EVAL(disp, ret); } +EGLSyncKHR EGLAPIENTRY +eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list) +{ + return _eglCreateSync(dpy, type, attrib_list, NULL, EGL_FALSE); +} + + +EGLSyncKHR EGLAPIENTRY +eglCreateSync64KHR(EGLDisplay dpy, EGLenum type, const EGLAttribKHR *attrib_list) +{ + return _eglCreateSync(dpy, type, NULL, attrib_list, EGL_TRUE); +} + + EGLBoolean EGLAPIENTRY eglDestroySyncKHR(EGLDisplay dpy, EGLSyncKHR sync) { diff --git a/src/egl/main/eglapi.h b/src/egl/main/eglapi.h index 7462b35..5226886 100644 --- a/src/egl/main/eglapi.h +++ b/src/egl/main/eglapi.h @@ -102,7 +102,7 @@ typedef _EGLImage *(*CreateImageKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLCo typedef EGLBoolean (*DestroyImageKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLImage *image); -typedef _EGLSync *(*CreateSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, EGLenum type, const EGLint *attrib_list); +typedef _EGLSync *(*CreateSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, EGLenum type, const EGLint *attrib_list, const EGLAttribKHR *attrib_list64); typedef EGLBoolean (*DestroySyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync); typedef EGLint (*ClientWaitSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, EGLint flags, EGLTimeKHR timeout); typedef EGLint (*WaitSyncKHR_t)(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync); diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h index 70381bc..b6b9ed8 100644 --- a/src/egl/main/egldisplay.h +++ b/src/egl/main/egldisplay.h @@ -107,6 +107,7 @@ struct _egl_extensions EGLBoolean KHR_reusable_sync; EGLBoolean KHR_fence_sync; EGLBoolean KHR_wait_sync; + EGLBoolean KHR_cl_event2; EGLBoolean KHR_surfaceless_context; EGLBoolean KHR_create_context; diff --git a/src/egl/main/eglsync.c b/src/egl/main/eglsync.c index 9d0067c..3b4a889 100644 --- a/src/egl/main/eglsync.c +++ b/src/egl/main/eglsync.c @@ -65,25 +65,76 @@ _eglParseSyncAttribList(_EGLSync *sync, const EGLint *attrib_list) } +static EGLint +_eglParseSyncAttribList64(_EGLSync *sync, const EGLAttribKHR *attrib_list) +{ + EGLint i, err = EGL_SUCCESS; + + if (!attrib_list) + return EGL_SUCCESS; + + for (i = 0; attrib_list[i] != EGL_NONE; i++) { + EGLint attr = attrib_list[i++]; + EGLint val = attrib_list[i]; + + switch (attr) { + case EGL_CL_EVENT_HANDLE_KHR: + if (sync->Type == EGL_SYNC_CL_EVENT_KHR) { + sync->CLEvent = val; + break; + } + /* fall through */ + default: + (void) val; + err = EGL_BAD_ATTRIBUTE; + break; + } + + if (err != EGL_SUCCESS) { + _eglLog(_EGL_DEBUG, "bad sync attribute 0x%04x", attr); + break; + } + } + + return err; +} + + EGLBoolean _eglInitSync(_EGLSync *sync, _EGLDisplay *dpy, EGLenum type, - const EGLint *attrib_list) + const EGLint *attrib_list, const EGLAttribKHR *attrib_list64) { EGLint err; if (!(type == EGL_SYNC_REUSABLE_KHR && dpy->Extensions.KHR_reusable_sync) && - !(type == EGL_SYNC_FENCE_KHR && dpy->Extensions.KHR_fence_sync)) + !(type == EGL_SYNC_FENCE_KHR && dpy->Extensions.KHR_fence_sync) && + !(type == EGL_SYNC_CL_EVENT_KHR && dpy->Extensions.KHR_cl_event2 && + attrib_list64)) return _eglError(EGL_BAD_ATTRIBUTE, "eglCreateSyncKHR"); _eglInitResource(&sync->Resource, sizeof(*sync), dpy); sync->Type = type; sync->SyncStatus = EGL_UNSIGNALED_KHR; - sync->SyncCondition = EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR; - err = _eglParseSyncAttribList(sync, attrib_list); + switch (type) { + case EGL_SYNC_CL_EVENT_KHR: + sync->SyncCondition = EGL_SYNC_CL_EVENT_COMPLETE_KHR; + break; + default: + sync->SyncCondition = EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR; + } + + if (attrib_list64) + err = _eglParseSyncAttribList64(sync, attrib_list64); + else + err = _eglParseSyncAttribList(sync, attrib_list); + if (err != EGL_SUCCESS) return _eglError(err, "eglCreateSyncKHR"); + if (type == EGL_SYNC_CL_EVENT_KHR && !sync->CLEvent) + return _eglError(EGL_BAD_ATTRIBUTE, "eglCreateSyncKHR"); + return EGL_TRUE; } @@ -103,7 +154,8 @@ _eglGetSyncAttribKHR(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, *value = sync->SyncStatus; break; case EGL_SYNC_CONDITION_KHR: - if (sync->Type != EGL_SYNC_FENCE_KHR) + if (sync->Type != EGL_SYNC_FENCE_KHR && + sync->Type != EGL_SYNC_CL_EVENT_KHR) return _eglError(EGL_BAD_ATTRIBUTE, "eglGetSyncAttribKHR"); *value = sync->SyncCondition; break; diff --git a/src/egl/main/eglsync.h b/src/egl/main/eglsync.h index c6cf8c6..1d2eb11 100644 --- a/src/egl/main/eglsync.h +++ b/src/egl/main/eglsync.h @@ -47,12 +47,13 @@ struct _egl_sync EGLenum Type; EGLenum SyncStatus; EGLenum SyncCondition; + EGLAttribKHR CLEvent; }; extern EGLBoolean _eglInitSync(_EGLSync *sync, _EGLDisplay *dpy, EGLenum type, - const EGLint *attrib_list); + const EGLint *attrib_list, const EGLAttribKHR *attrib_list64); extern EGLBoolean From mareko at kemper.freedesktop.org Thu Apr 30 12:43:15 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:15 -0700 (PDT) Subject: Mesa (master): egl/dri2: return the latest sync status in eglGetSyncAttribKHR Message-ID: <20150430124315.DD583761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: a2557b30d843d4f3dada6a022f27e8343adabca8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2557b30d843d4f3dada6a022f27e8343adabca8 Author: Marek Ol??k Date: Fri Apr 10 23:35:39 2015 +0200 egl/dri2: return the latest sync status in eglGetSyncAttribKHR --- src/egl/main/eglsync.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/egl/main/eglsync.c b/src/egl/main/eglsync.c index 3b4a889..8b8ab16 100644 --- a/src/egl/main/eglsync.c +++ b/src/egl/main/eglsync.c @@ -30,6 +30,7 @@ #include "eglsync.h" #include "eglcurrent.h" +#include "egldriver.h" #include "egllog.h" @@ -144,13 +145,19 @@ _eglGetSyncAttribKHR(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync, EGLint attribute, EGLint *value) { if (!value) - return _eglError(EGL_BAD_PARAMETER, "eglGetConfigs"); + return _eglError(EGL_BAD_PARAMETER, "eglGetSyncAttribKHR"); switch (attribute) { case EGL_SYNC_TYPE_KHR: *value = sync->Type; break; case EGL_SYNC_STATUS_KHR: + /* update the sync status */ + if (sync->SyncStatus != EGL_SIGNALED_KHR && + (sync->Type == EGL_SYNC_FENCE_KHR || + sync->Type == EGL_SYNC_CL_EVENT_KHR)) + drv->API.ClientWaitSyncKHR(drv, dpy, sync, 0, 0); + *value = sync->SyncStatus; break; case EGL_SYNC_CONDITION_KHR: From mareko at kemper.freedesktop.org Thu Apr 30 12:43:15 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:15 -0700 (PDT) Subject: Mesa (master): gallium,clover: add OpenCL interoperability support for CL events Message-ID: <20150430124315.F2CA0761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 952b5e84db47be3adaf01f047efeedd26cf0d173 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=952b5e84db47be3adaf01f047efeedd26cf0d173 Author: Marek Ol??k Date: Fri Apr 10 18:42:42 2015 +0200 gallium,clover: add OpenCL interoperability support for CL events v2: - move interop.cpp to clover/api - change intptr_t to void* in the interface - add a virtual function fence() to simplify some code v3: - use bool in the interface v4: - enclose the last two interop functions in try..catch Reviewed-by: Francisco Jerez --- src/gallium/include/state_tracker/opencl_interop.h | 40 ++++++++++++ src/gallium/state_trackers/clover/Makefile.sources | 1 + src/gallium/state_trackers/clover/api/interop.cpp | 64 ++++++++++++++++++++ src/gallium/state_trackers/clover/core/event.hpp | 8 +++ src/gallium/targets/opencl/opencl.sym | 1 + 5 files changed, 114 insertions(+) diff --git a/src/gallium/include/state_tracker/opencl_interop.h b/src/gallium/include/state_tracker/opencl_interop.h new file mode 100644 index 0000000..4983644 --- /dev/null +++ b/src/gallium/include/state_tracker/opencl_interop.h @@ -0,0 +1,40 @@ +/************************************************************************** + * + * Copyright 2015 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#ifndef OPENCL_INTEROP_H +#define OPENCL_INTEROP_H + +/* dlsym these without the "_t" suffix. You should get the correct symbols + * if the OpenCL driver is loaded. + */ + +typedef bool (*opencl_dri_event_add_ref_t)(void *cl_event); +typedef bool (*opencl_dri_event_release_t)(void *cl_event); +typedef bool (*opencl_dri_event_wait_t)(void *cl_event, uint64_t timeout); +typedef struct pipe_fence_handle *(*opencl_dri_event_get_fence_t)(void *cl_event); + +#endif /* OPENCL_INTEROP_H */ diff --git a/src/gallium/state_trackers/clover/Makefile.sources b/src/gallium/state_trackers/clover/Makefile.sources index fa96774..10bbda0 100644 --- a/src/gallium/state_trackers/clover/Makefile.sources +++ b/src/gallium/state_trackers/clover/Makefile.sources @@ -4,6 +4,7 @@ CPP_SOURCES := \ api/dispatch.cpp \ api/dispatch.hpp \ api/event.cpp \ + api/interop.cpp \ api/kernel.cpp \ api/memory.cpp \ api/platform.cpp \ diff --git a/src/gallium/state_trackers/clover/api/interop.cpp b/src/gallium/state_trackers/clover/api/interop.cpp new file mode 100644 index 0000000..ea0c7c7 --- /dev/null +++ b/src/gallium/state_trackers/clover/api/interop.cpp @@ -0,0 +1,64 @@ +// +// Copyright 2015 Advanced Micro Devices, Inc. +// All Rights Reserved. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +// OTHER DEALINGS IN THE SOFTWARE. +// + +#include "core/event.hpp" +#include "api/util.hpp" + +using namespace clover; + +extern "C" { + +PUBLIC bool +opencl_dri_event_add_ref(cl_event event) +{ + return clRetainEvent(event) == CL_SUCCESS; +} + +PUBLIC bool +opencl_dri_event_release(cl_event event) +{ + return clReleaseEvent(event) == CL_SUCCESS; +} + +PUBLIC bool +opencl_dri_event_wait(cl_event event, uint64_t timeout) try { + if (!timeout) { + return obj(event).status() == CL_COMPLETE; + } + + obj(event).wait(); + return true; + +} catch (error &) { + return false; +} + +PUBLIC struct pipe_fence_handle * +opencl_dri_event_get_fence(cl_event event) try { + return obj(event).fence(); + +} catch (error &) { + return NULL; +} + +} diff --git a/src/gallium/state_trackers/clover/core/event.hpp b/src/gallium/state_trackers/clover/core/event.hpp index 0e1359a..d407c80 100644 --- a/src/gallium/state_trackers/clover/core/event.hpp +++ b/src/gallium/state_trackers/clover/core/event.hpp @@ -70,6 +70,10 @@ namespace clover { virtual cl_command_type command() const = 0; virtual void wait() const = 0; + virtual struct pipe_fence_handle *fence() const { + return NULL; + } + const intrusive_ref context; protected: @@ -116,6 +120,10 @@ namespace clover { friend class command_queue; + virtual struct pipe_fence_handle *fence() const { + return _fence; + } + private: virtual void fence(pipe_fence_handle *fence); action profile(command_queue &q, const action &action) const; diff --git a/src/gallium/targets/opencl/opencl.sym b/src/gallium/targets/opencl/opencl.sym index ee8aacf..9fcc576 100644 --- a/src/gallium/targets/opencl/opencl.sym +++ b/src/gallium/targets/opencl/opencl.sym @@ -1,6 +1,7 @@ { global: cl*; + opencl_dri_*; local: *; }; From mareko at kemper.freedesktop.org Thu Apr 30 12:43:16 2015 From: mareko at kemper.freedesktop.org (Marek Olšák) Date: Thu, 30 Apr 2015 05:43:16 -0700 (PDT) Subject: Mesa (master): docs/relnotes: document the new EGL sync extensions Message-ID: <20150430124316.12DAA761E9@kemper.freedesktop.org> Module: Mesa Branch: master Commit: 1db5d3c19ee8d91686dfe3c1927a3e2dfa83830c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1db5d3c19ee8d91686dfe3c1927a3e2dfa83830c Author: Marek Ol??k Date: Wed Apr 29 20:33:21 2015 +0200 docs/relnotes: document the new EGL sync extensions --- docs/relnotes/10.6.0.html | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/relnotes/10.6.0.html b/docs/relnotes/10.6.0.html index ff24842..fbc4d5b 100644 --- a/docs/relnotes/10.6.0.html +++ b/docs/relnotes/10.6.0.html @@ -58,6 +58,10 @@ Note: some of the new features are only available with certain drivers.

GL_ARB_texture_stencil8 on nv50, nvc0, r600, radeonsi, softpipe

GL_ARB_uniform_buffer_object on freedreno

GL_EXT_draw_buffers2 on freedreno

GL_OES_EGL_sync on all drivers

EGL_KHR_fence_sync on freedreno, nv50, nvc0, r600, radeonsi

EGL_KHR_wait_sync on freedreno, nv50, nvc0, r600, radeonsi

EGL_KHR_cl_event2 on freedreno, nv50, nvc0, r600, radeonsi

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Mesa 10.5.3 Release Notes / April 12, 2015

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3.6 How can I change the maximum framebuffer size in Mesa's -swrast backend?

The Mesa 3D Graphics Library

Mesa 10.5.3 Release Notes / April 12, 2015

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The Mesa 3D Graphics Library

Mesa 10.5.4 Release Notes / April 24, 2015

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The Mesa 3D Graphics Library

Mesa 10.5.4 Release Notes / April 24, 2015

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3.6 How can I change the maximum framebuffer size in Mesa's -`swrast` backend?