Mesa (master): i965: Don' t set NirOptions for stages that will use the vec4 backend.

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: c2a0600d5b0645533ba442b5ab879b23c2564a4d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2a0600d5b0645533ba442b5ab879b23c2564a4d

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Apr  9 23:26:49 2015 -0700

i965: Don't set NirOptions for stages that will use the vec4 backend.

We've started using NirOptions != NULL to mean "we're using NIR for this
stage."  However, when INTEL_USE_NIR=1, we set it for a bunch of stages
that still use the vec4 backend, and thus definitely aren't using NIR.

For example, if INTEL_USE_NIR=1 we disable the GLSL IR cubemap
normalization pass, even for vertex shaders and geometry shaders.  This
is wrong, but breaks a very uncommon case.

When I started deleting GLSL IR for stages where we claimed to be using
NIR, this bug quickly became apparent.

For now, only set it for fragment shaders, and vertex shaders if
brw->scalar_vs is set.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

---

 src/mesa/drivers/dri/i965/brw_context.c |   15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index f0de711..dfd0031 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -560,12 +560,6 @@ brw_initialize_context_constants(struct brw_context *brw)
       .lower_ffma = true,
    };
 
-   bool use_nir_default[MESA_SHADER_STAGES];
-   use_nir_default[MESA_SHADER_VERTEX] = false;
-   use_nir_default[MESA_SHADER_GEOMETRY] = false;
-   use_nir_default[MESA_SHADER_FRAGMENT] = false;
-   use_nir_default[MESA_SHADER_COMPUTE] = false;
-
    /* We want the GLSL compiler to emit code that uses condition codes */
    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
       ctx->Const.ShaderCompilerOptions[i].MaxIfDepth = brw->gen < 6 ? 16 : UINT_MAX;
@@ -579,9 +573,6 @@ brw_initialize_context_constants(struct brw_context *brw)
 	 (i == MESA_SHADER_FRAGMENT);
       ctx->Const.ShaderCompilerOptions[i].EmitNoIndirectUniform = false;
       ctx->Const.ShaderCompilerOptions[i].LowerClipDistance = true;
-
-      if (brw_env_var_as_boolean("INTEL_USE_NIR", use_nir_default[i]))
-         ctx->Const.ShaderCompilerOptions[i].NirOptions = &nir_options;
    }
 
    ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = true;
@@ -594,8 +585,14 @@ brw_initialize_context_constants(struct brw_context *brw)
       ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitNoIndirectOutput = true;
       ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitNoIndirectTemp = true;
       ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = false;
+
+      if (brw_env_var_as_boolean("INTEL_USE_NIR", false))
+         ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].NirOptions = &nir_options;
    }
 
+   if (brw_env_var_as_boolean("INTEL_USE_NIR", false))
+      ctx->Const.ShaderCompilerOptions[MESA_SHADER_FRAGMENT].NirOptions = &nir_options;
+
    /* ARB_viewport_array */
    if (brw->gen >= 7 && ctx->API == API_OPENGL_CORE) {
       ctx->Const.MaxViewports = GEN7_NUM_VIEWPORTS;