Mesa (10.3): nv50/ir: fix texture offsets in release builds
Emil Velikov
evelikov at kemper.freedesktop.org
Mon Jan 12 08:43:00 UTC 2015
Module: Mesa
Branch: 10.3
Commit: 9bfdf3ae515d78c39d49174a9dcf4ae5767c74b5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bfdf3ae515d78c39d49174a9dcf4ae5767c74b5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jan 4 18:03:20 2015 -0500
nv50/ir: fix texture offsets in release builds
assert's get compiled out in release builds, so they can't be relied
upon to perform logic.
Reported-by: Pierre Moreau <pierre.morrow at free.fr>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Roy Spliet <rspliet at eclipso.eu>
Cc: "10.2 10.3 10.4" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit fb1afd1ea5fd25d82c75c5c3a2aba0bcb53b6d47)
---
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 3 ++-
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index e283424..0d7612e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -772,7 +772,8 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
if (i->tex.useOffsets) {
for (int c = 0; c < 3; ++c) {
ImmediateValue val;
- assert(i->offset[0][c].getImmediate(val));
+ if (!i->offset[0][c].getImmediate(val))
+ assert(!"non-immediate offset");
i->tex.offset[c] = val.reg.data.u32;
i->offset[0][c].set(NULL);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 31ff56c..9f0b619 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -760,7 +760,8 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
assert(i->tex.useOffsets == 1);
for (c = 0; c < 3; ++c) {
ImmediateValue val;
- assert(i->offset[0][c].getImmediate(val));
+ if (!i->offset[0][c].getImmediate(val))
+ assert(!"non-immediate offset passed to non-TXG");
imm |= (val.reg.data.u32 & 0xf) << (c * 4);
}
if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {
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