Mesa (master): nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capability

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 1087c566e3496d08fe70bc0725073e3022716dc5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1087c566e3496d08fe70bc0725073e3022716dc5

Author: Alexandre Courbot <acourbot at nvidia.com>
Date:   Thu Jul  2 11:36:55 2015 +0900

nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capability

Prefer blit-based texture transfers only if the chip has dedicated VRAM
since it would translate to a copy into the same memory on shared-memory
chips.

Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
Reported-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 95e246b..3f52c85 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -163,7 +163,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_USER_CONSTANT_BUFFERS:
    case PIPE_CAP_USER_INDEX_BUFFERS:
    case PIPE_CAP_USER_VERTEX_BUFFERS:
-   case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
    case PIPE_CAP_TEXTURE_QUERY_LOD:
    case PIPE_CAP_SAMPLE_SHADING:
    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
@@ -179,6 +178,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
    case PIPE_CAP_COMPUTE:
       return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
+   case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+      return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 
    /* unsupported caps */
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: