Mesa (master): i965: Reserve more batch space to accomodate Gen6 perfmonitors.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: d9ab95b365f058a46bc43a8cb96b6fff10a13faf
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9ab95b365f058a46bc43a8cb96b6fff10a13faf

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Mar  4 15:46:57 2015 -0800

i965: Reserve more batch space to accomodate Gen6 perfmonitors.

Ben noticed that I said each PIPE_CONTROL was 4 DWords, but it's
actually 5 DWords on Gen6-7.  We've been reserving insufficient space
for performance monitoring on Sandybridge, which means it would likely
break if you used that functionality.  (Thankfully, no one does...)

Also, the existing number of 146 was the result of me flubbing up the
arithmetic: it should have actually been 140.

Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

---

 src/mesa/drivers/dri/i965/intel_batchbuffer.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index ef8a6ff..fdd07e0 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -22,12 +22,12 @@ extern "C" {
  *   - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
  *   - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
  *     - Two sets of PIPE_CONTROLs, which become 3 PIPE_CONTROLs each on SNB,
- *       which are 4 DWords each ==> 2 * 3 * 4 * 4 = 96 bytes
+ *       which are 5 DWords each ==> 2 * 3 * 5 * 4 = 120 bytes
  *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
  *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
  *       Sandybridge PIPE_CONTROL madness.
  */
-#define BATCH_RESERVED 146
+#define BATCH_RESERVED 152
 
 struct intel_batchbuffer;