Mesa (master): radeonsi: ubo indexing support (v2)
Dave Airlie
airlied at kemper.freedesktop.org
Sat Jul 25 00:07:35 UTC 2015
Module: Mesa
Branch: master
Commit: 7b40d92f0d0661c05c1afa59555905b2c37e594f
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b40d92f0d0661c05c1afa59555905b2c37e594f
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jul 13 09:12:18 2015 +0100
radeonsi: ubo indexing support (v2)
This is required as part of ARB_gpu_shader5.
no backend changes are required for this, or if
any are, it's the same ones as for samplers.
v2: use get_indirect_index (Marek)
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
docs/GL3.txt | 2 +-
src/gallium/drivers/radeonsi/si_shader.c | 15 ++++++++++++---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 1f2771a..e3fa1a1 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -99,7 +99,7 @@ GL 4.0, GLSL 4.00:
GL_ARB_gpu_shader5 DONE (i965, nvc0)
- 'precise' qualifier DONE
- Dynamically uniform sampler array indices DONE (r600, radeonsi, softpipe)
- - Dynamically uniform UBO array indices DONE (r600)
+ - Dynamically uniform UBO array indices DONE (r600, radeonsi)
- Implicit signed -> unsigned conversions DONE
- Fused multiply-add DONE ()
- Packing/bitfield/conversion functions DONE (r600, radeonsi, softpipe)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index d4a7d3b..81f7bdb 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1191,7 +1191,7 @@ static LLVMValueRef fetch_constant(
const struct tgsi_ind_register *ireg = ®->Indirect;
unsigned buf, idx;
- LLVMValueRef addr;
+ LLVMValueRef addr, bufp;
LLVMValueRef result;
if (swizzle == LP_CHAN_ALL) {
@@ -1206,7 +1206,7 @@ static LLVMValueRef fetch_constant(
buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
idx = reg->Register.Index * 4 + swizzle;
- if (!reg->Register.Indirect) {
+ if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
if (type != TGSI_TYPE_DOUBLE)
return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
else {
@@ -1216,13 +1216,22 @@ static LLVMValueRef fetch_constant(
}
}
+ if (reg->Register.Dimension && reg->Dimension.Indirect) {
+ LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+ LLVMValueRef index;
+ index = get_indirect_index(si_shader_ctx, ®->DimIndirect,
+ reg->Dimension.Index);
+ bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
+ } else
+ bufp = si_shader_ctx->const_resource[buf];
+
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
addr = lp_build_add(&bld_base->uint_bld, addr,
lp_build_const_int32(base->gallivm, idx * 4));
- result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
+ result = buffer_load_const(base->gallivm->builder, bufp,
addr, bld_base->base.elem_type);
if (type != TGSI_TYPE_DOUBLE)
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