Mesa (master): nvc0/ir: trim out barrier sync for non-compute shaders

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 313940b03cf7c857143b9e3ec0ab969ce4472c83
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=313940b03cf7c857143b9e3ec0ab969ce4472c83

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Tue Jul 28 02:37:51 2015 -0400

nvc0/ir: trim out barrier sync for non-compute shaders

It seems like they're never necessary, and actively cause harm. This
fixes some of the barrier-related piglits.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 710f53d..c632e30 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -559,6 +559,12 @@ NVC0LegalizePostRA::visit(BasicBlock *bb)
       } else
       if (i->isNop()) {
          bb->remove(i);
+      } else
+      if (i->op == OP_BAR && i->subOp == NV50_IR_SUBOP_BAR_SYNC &&
+          prog->getType() != Program::TYPE_COMPUTE) {
+         // It seems like barriers are never required for tessellation since
+         // the warp size is 32, and there are always at most 32 tcs threads.
+         bb->remove(i);
       } else {
          // TODO: Move this to before register allocation for operations that
          // need the $c register !