Mesa (master): 56 new commits
Francisco Jerez
currojerez at kemper.freedesktop.org
Wed Jul 29 12:28:35 UTC 2015
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e645e68d6672cac2872fa509fb22bc2581f4b67
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:18:51 2015 +0300
i965/fs: Switch opt_cse() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=992cda2c8a452ec86386a0f98eaf522afe206695
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:41:18 2015 +0300
i965/fs: Switch lower_logical_sends() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=930ebb258524762c765fa864ef7063bd8bb754a1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:34:43 2015 +0300
i965/fs: Switch lower_load_payload() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0b192d3d9fa64f6f8bff5f1e456e40e72f4875e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 20:14:41 2015 +0300
i965/fs: Don't rely on the default builder to create a null register in emit_spill.
It's not guaranteed to have the same width as the instruction
generating the spilled variable.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfad71606a987f14f20d2c3607846648f8537f2b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:15:44 2015 +0300
i965/fs: Set up the builder execution size explicitly in opt_sampler_eot().
opt_sampler_eot() was relying on the default builder to have the same
width as the sampler and FB write opcodes it was eliminating, the
channel selects didn't matter because the builder was only being used
to allocate registers, no new instructions were being emitted with it.
A future commit will change the width of the default builder what will
break this assumption, so initialize it explicitly here.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=09039f4bc120481219d01ed17e1552ca8ad66455
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:20:50 2015 +0300
i965/fs: Initialize a builder explicitly in opt_peephole_predicated_break().
This wasn't taking into account the execution controls of the original
instruction, but it was most likely not a bug because control flow
instructions are typically full width.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1f4724097d1074ec9afdc9ce9ad024add125923
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:27:30 2015 +0300
i965/fs: Set execution controls explicitly in opt_peephole_sel().
Emit the SELs and MOVs with the same execution controls as the
original MOVs, and the CMP with the same execution controls as the IF.
Also explicitly check that the execution controls of any pair of MOVs
being folded into a SEL are compatible (which is almost always going
to be the case), since otherwise it would seem wrong to initialize the
builder object below from the then_mov instruction only.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff463af436bcf07430807512c9f0bf0f627288ce
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:38:59 2015 +0300
i965/fs: Set execution controls correctly in lower_integer_multiplication().
lower_integer_multiplication() was ignoring the execution controls of
the original MUL instruction. Fix it by using the new fs_builder
constructor.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce90227c71c8cbe6ca4317f1873ff12c70081c4c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 17:55:49 2015 +0300
i965/fs: Set execution controls correctly for lowered pull constant loads.
demote_pull_constants() was ignoring the execution size and channel
selects of the instruction that wanted the constant, which doesn't
matter for uniform pull constant loads because all channels get the
same scalar value, but it might for varying pull constant loads. Fix
it by using the new fs_builder() constructor that takes care of
setting execution controls compatible with the instruction passed as
argument.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53077aee6670022e634a4775d8abbb59c458b7d7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:09:45 2015 +0300
i965/fs: Set the execution size of the MOVs correctly in opt_combine_constants().
The execution size was being left equal to the default of 8/16, which
AFAICT would have overwritten components other than the one we wanted
to initialize and could potentially have corrupted other registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f7dea0b3212aa4ce49fcf9e94bf7aab130eeab2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 17:54:46 2015 +0300
i965/fs: Define a new fs_builder constructor taking an instruction as argument.
We have a number of optimization passes that repeat the same pattern
before inserting new instructions into the program based on some
previous instruction: They point the default builder at the original
instruction, then call exec_all() and group() to select the same
execution controls the original instruction had, and then maybe call
annotate() to clone the debug annotation from the original
instruction.
In fact an optimization pass missing any of these steps is likely to
be broken if the intention was to emit new code based on a preexisting
instruction, so let's make it easy for passes to do the right thing by
having an fs_builder constructor that automates the task of setting up
a builder to emit a given instruction provided as argument.
The following patches fix all cases I've found in which we weren't
explicitly initializing the execution controls of the emitted
instructions, and clean-up optimization passes which were already
doing the right thing to use the new constructor.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cb60d770fc24bf00b6f7e5898cca1426e55c026
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 16:25:55 2015 +0300
i965/fs: Translate memory barrier NIR intrinsics.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5f1a48e234d47b24df38cb562cffb8941d43795
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Jun 28 21:15:28 2015 +0300
i965/fs: Execute nir_setup_uniforms, _inputs and _outputs unconditionally.
Images take up zero uniform slots in the nir_shader::num_uniforms
calculation, but nir_setup_uniforms needs to be executed even if the
program has no non-image uniforms so the driver-specific image
parameters are uploaded. nir_setup_uniforms is a no-op if there are
really no uniforms, so checking the num_uniform count is useless in
any case.
The nir_setup_inputs and _outputs changes shouldn't lead to any
functional change, they are just meant to preserve the symmetry
between them and nir_setup_uniforms.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e5a90792d14aeb599dd236f830e6e344b35c905
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 22:12:03 2015 +0300
i965/fs: Don't overwrite fs_visitor::uniforms and ::param_size during the SIMD16 run.
Image variables need to allocate additional uniform slots over
nir_shader::num_uniforms. nir_setup_uniforms() overwrites the values
imported from the SIMD8 visitor and then exits early before entering
the nir_shader::uniforms loop, so image uniforms are never re-created.
Instead leave the imported values alone, they *must* be the same for
the uniform layout of both runs to be compatible.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea0ac53f059c418d5797c495b87020f2ca2ec842
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jun 29 16:50:49 2015 +0300
i965/fs: Drop unused untyped surface read and atomic emit methods.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=854c4d8b37416d3e5593099a8e5441f3cf861173
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 20:52:58 2015 +0300
i965/fs: Revisit NIR atomic counter intrinsic translation.
Rewrite the NIR atomic counter intrinsics translation code making use
of the recently introduced surface builder. This will allow the
removal of some of the functionality duplicated between the visitor
and surface builder.
v2: Drop VEC4 suport.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1aab58f39450213ea2ac43549eefb8acd1e6584a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 30 19:31:44 2015 +0300
i965/fs: Import surface message builder helper functions.
Implement helper functions that can be used to construct and send
untyped and typed surface read, write and atomic messages to the
shared dataport unit easily.
v2: Drop VEC4 suport.
v3: Reimplement in terms of logical send opcodes.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03846696ce2deaaaff42b2acd7745b51a7f115f2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:39:03 2015 +0300
i965/fs: Handle zero-size allocations in fs_builder::vgrf().
This will be handy to avoid some ugly ternary operators in the next
patch, like:
fs_reg reg = (size == 0 ? null_reg_ud() : vgrf(..., size));
Because a zero-size register allocation is guaranteed not to ever be
read or written we can just return the null register. Another
possibility would be to actually allocate a zero-size VGRF what would
involve defining a zero-size register class in the register allocator
and a considerable amount of churn.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3352724dfa4eb5c93290db92ae99d26d9b89e630
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 14 18:42:57 2015 +0300
i965/fs: Implement lowering of logical surface instructions.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=086d29f4d747bbcfe37beeb18ba77fb2cb84dbdc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jul 18 16:16:19 2015 +0300
i965/fs: Hook up SIMD lowering to unroll surface instructions of unsupported width.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a594a95a930f1658062e4d86d0f37d491b372b3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 21 18:45:32 2015 +0300
i965/fs: Define logical typed and untyped surface opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects its arguments
separately as individual sources, like:
typed_surface_write_logical null, coordinates, source, surface,
num_coordinates, num_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mainly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3af2623da5167aa686bcb2cff01d27058a507026
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 20 17:38:15 2015 +0300
i965: Lift the constness restriction on surface indices passed to untyped ops.
v2: Update NIR atomic intrinsic handling too (Ken).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0c02d2bbb765b0e997ad524d8e51838e529d9c0
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Jun 28 21:04:17 2015 +0300
i965: Define the setup_vector_uniform_values() backend_visitor interface.
This cleans up the VEC4 implementation of setup_uniform_values()
somewhat and will avoid duplication of the image uniform upload code
by having a common interface to upload a vector of uniforms on either
back-end.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd0d6a9cce8b28357888bb261fac639e2833c51f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 24 16:51:14 2015 +0300
i965/fs: Remove the emit_texture_gen*() fs_visitor methods.
This is now dead code.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59979b133dd16bf46803f87e78677eba944cc757
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 17 18:23:31 2015 +0300
i965/fs: Reimplement emit_mcs_fetch() in terms of logical sends.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba78a5007171afaa5f2d76d71be131f01a5b5023
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 16:07:45 2015 +0300
i965/fs: Reimplement emit_texture() in terms of logical send messages.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4be99438e6e40280f9dc071882ce3bfbfabadb4a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 21:19:52 2015 +0300
i965/fs: Hook up SIMD lowering to handle texturing opcodes of unsupported width.
This should match the set of cases in which we currently call fail()
or no16() from the emit_texture_*() methods and the ones in which
emit_texture_gen4() enables the SIMD16 workaround.
Hint for reviewers: It's not a big deal if I happen to have missed
some case here, it will just lead to an assertion failure down the
road which is easily fixable, however being stricter than necessary
won't cause any visible breakage, it would just decrease performance
silently due to the unnecessary message splitting, so feel free to
double-check that all cases listed here already cause a SIMD8/16
fall-back with the current texturing code -- You may want to skip over
the Gen5-6 cases though if you don't have pencil and paper at hand.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cd466f6c3192015ea1794afc57eb453d7f13818
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jul 18 17:09:37 2015 +0300
i965/fs: Implement lowering of logical texturing opcodes on Gen4.
Unlike its Gen5 and Gen7 counterparts this patch isn't a plain
refactor of the previous Gen4 texturing code, it's more of a rewrite
largely based on emit_texture_gen4_simd16(). The reason is that on
the one hand the original emit_texture_gen4() code didn't seem easily
fixable to be SIMD width-invariant and had plenty of clutter to
support SIMD-width workarounds which are no longer required. On the
other hand emit_texture_gen4_simd16() was missing a number of
SIMD8-only opcodes. This should generalize both and roughly match
their current behaviour where there is overlap.
Incidentally this will fix the following piglits on Gen4:
arb_shader_texture_lod.execution.arb_shader_texture_lod-texgrad
arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 2d
arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 3d
arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d
arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d_projvec4
arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 3d
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=501134b9fe02633ca0cdda66a9b670ae38e791f7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jul 18 16:52:06 2015 +0300
i965/fs: Implement lowering of logical texturing opcodes on Gen5-6.
This should be largely equivalent to emit_texture_gen5() except for
slight codestyle changes and the use i965 opcodes instead of the
ir_texture_opcode enum, see "i965/fs: Implement lowering of logical
texturing opcodes on Gen7+." for the mapping between them.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03582f95b256e483fc1b0d78bd6a49203a448a23
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 17 18:50:27 2015 +0300
i965/fs: Lower SHADER_OPCODE_TXF_UMS/MCS_LOGICAL too on Gen7+.
These weren't being handled by emit_texture_gen7() but we can easily
lower them here for consistency with other texturing opcodes.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8be01e3548bdd900b7cadb5c9a77e52b01151cfe
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 18:08:51 2015 +0300
i965/fs: Implement lowering of logical texturing opcodes on Gen7+.
This should be largely equivalent to emit_texture_gen7() except that
we now get i965 sampling opcodes directly rather than
ir_texture_opcode enum values. The mapping is as follows:
- ir_tex -> SHADER_OPCODE_TEX
- ir_txb -> FS_OPCODE_TXB
- ir_txl -> SHADER_OPCODE_TXL
- ir_txd -> SHADER_OPCODE_TXD
- ir_txf -> SHADER_OPCODE_TXF
- ir_txf_ms -> SHADER_OPCODE_TXF_CMS
- ir_txs -> SHADER_OPCODE_TXS
- ir_query_levels -> SHADER_OPCODE_TXS too, the visitor will make
sure that the provided lod value is zero in this
case.
- ir_lod -> SHADER_OPCODE_LOD
- ir_tg4 -> SHADER_OPCODE_TG4_OFFSET if the offset value is not
immediate, SHADER_OPCODE_TG4 otherwise.
Other than that there are only minor changes and style fixes like the
implementation now being factored out in static functions to improve
encapsulation.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a69332a31243a7733dab926b765964ba6df827b2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 24 16:41:19 2015 +0300
i965/fs: Fix misleading comment regarding the message header in emit_texture_gen7.
This hasn't been overallocating space for the header for a long time.
It still leaves the header uninitialized though until the generator
fixes it.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc2273a3400963e478582ee1efbfc8cdaae3eae7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 17 18:46:21 2015 +0300
i965/fs: Pass a BAD_FILE header source to LOAD_PAYLOAD in emit_texture_gen7().
So that it's left uninitialized by LOAD_PAYLOAD, we only need to
reserve space for it in the message since it will be initialized
implicitly by the generator.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=44a8cf488e0370d7e5abe363c1fd2d21247a6e32
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:33:04 2015 +0300
i965/fs: Fix opt_zero_samples() for texturing ops not matching dispatch_width.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fbb3d3569e6d353dee6e558eb9fd961b5a8a12c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:42:20 2015 +0300
i965/fs: Use exec_size instead of dispatch_width to determine the message variant.
dispatch_width is global for a single compilation and doesn't
necessarily match the desired execution width if we had to lower the
original full-width instruction due to hardware limitations. These
were all inside a Gen4-specific branch so this patch shouldn't have
any effect on more recent hardware.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33deff4f0582d2c073d34d4d6ec8344d2b1fbf7d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 21 18:42:27 2015 +0300
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f18792aa10cedba2034762eade816c4c77ca46c6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 16 16:12:48 2015 +0300
i965/fs: Reimplement emit_single_fb_write() in terms of logical framebuffer writes.
The only non-trivial thing it still has to do is figure out where to
take the src/dst depth values from and predicate the instruction if
discard is in use. The manual SIMD unrolling logic in the dual-source
case goes away because this is now handled transparently by the SIMD
lowering pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59e7e6f7a21f13ff8963cf21af2e969f1f7961f5
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 17:59:34 2015 +0300
i965/fs: Implement lowering of logical framebuffer writes.
This does essentially the same thing as
fs_visitor::emit_single_fb_write(), with some slight differences:
- We don't have to worry about exec_size and use_2nd_half anymore,
16-wide sources have already been lowered to 8-wide thanks to the
previous commit and the manual argument unzipping is no longer
required.
- The src/dst_depth and sample_mask values are now explicit sources
of the instruction instead of being taken from the visitor state
directly. The same goes for the kill-pixel mask that will be
passed to the instruction explicitly as predicate.
- Everything is now done in static functions to improve
encapsulation.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=633938afd349f2b423146969688c11f1e29ca17a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 21:19:28 2015 +0300
i965/fs: Hook up SIMD lowering to unroll FB writes of unsupported width.
This shouldn't have any effect because we don't emit logical
framebuffer writes yet.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cecf738b0fbe8ebafe304c717e847f1d3f41d3ca
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 14:49:27 2015 +0300
i965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.
This is now unused.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=98b0122e0a194e0d6c5d3eb05fd3f29a5286b3b3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 17:31:04 2015 +0300
i965/fs: Don't attempt to copy the useless half of oMask for SIMD8 FB writes.
There's no need to initialize the wrong half of oMask in the payload
when we're doing an 8-wide framebuffer write because it will be
ignored by the hardware anyway. By doing it this way we can let the
SIMD lowering pass split the sample_mask source as a regular
per-channel source, otherwise we would have to introduce some sort of
per-instruction source query or use fs_inst::header_size for the
lowering pass to be able to find out whether some source is
header-like, and leave the source untouched in that case.
As a bonus this achieves the same purpose as the previous code without
making use of the SET_OMASK pseudo-instruction, which will be removed
in a future commit.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1abfc49476f0277ddee0df269b56fc3de714c4b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 18:50:59 2015 +0300
i965/fs: Move up Gen6 no16 check to emit_fb_writes().
And update the comment.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b145855df624d0031eb2399503389948ebfcdd26
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 18:49:55 2015 +0300
i965/fs: Move up prog_data->uses_omask assignment up to brw_codegen_wm_prog().
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bd991a1377862e3b1b9c05e835289fff9d6785f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 17:05:27 2015 +0300
i965/fs: Simplify control flow in emit_single_fb_write().
Flatten the if ladder to match the way that the ordering of these
fields is specified in the hardware documentation a bit more closely.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ad928ed9f4e7723f709f91d18d17726c92f0b7b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 16:42:57 2015 +0300
i965/fs: Fix slight layering violation in emit_single_fb_writes().
In cases where the color0 argument wasn't being provided,
emit_single_fb_writes() would take the alpha channel directly from the
visitor state instead of taking it from its arguments. This sort of
hack didn't fit nicely into the logical send-message approach because
all parameters of the instruction have to be visible to the SIMD
lowering pass for it to be able to split them into halves at all.
Fix it by using LOAD_PAYLOAD in fs_visitor::emit_fb_writes() to
provide an actual color0 vector with undefined contents except for the
alpha component to match the previous behavior when no color buffers
are enabled.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f68ec2baf49e37f9ce4fffe95f13177eb7225015
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:40:18 2015 +0300
i965/fs: Make sure that the type sizes are compatible during copy propagation.
It's surprising that we weren't checking for this already. A future
patch will cause code like the following to be emitted:
MOV(16) tmp<1>:uw, src
MOV(8) dst<1>:ud, tmp<8,8,1>:ud
The second MOV comes from the expansion of a LOAD_PAYLOAD header copy,
so I don't have control over its types. Copy propagation will happily
turn this into:
MOV(8) dst<1>:ud, src
Which has different semantics. Fix it by preventing propagation in
cases where a single channel of the instruction would span several
channels of the copy (this requirement could in fact be relaxed if the
copy is just a trivial memcpy, but this case is unusual enough that I
don't think it matters in practice).
I'm deliberately only checking if the type of the instruction is
larger than the original, because the converse case seems to be
handled correctly already in the code below.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa75f2d56616cba81014d4fc02931dcfaedaf5b9
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:41:34 2015 +0300
i965/fs: Honour the instruction force_sechalf and exec_size fields for FB writes.
We were previously guessing the half based on the EOT flag which seems
rather gross.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9f31a032b0a1068a4e2ceed9ed4680ecf13e28b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 16:14:36 2015 +0300
i965/fs: Define logical framebuffer write opcode.
The logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects its arguments
that make up the payload separately as individual sources, like:
fb_write_logical null, color0, color1, src0_alpha,
src_depth, dst_depth, sample_mask, num_components
This patch defines the opcode and usual instruction boilerplate,
including a placeholder lowering function provided mainly as
self-documentation.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8368939e5d94f8d4ae55a1f22a755922ee77132b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 21:15:31 2015 +0300
i965/fs: Implement pass to lower instructions of unsupported SIMD width.
This lowering pass implements an algorithm to expand SIMDN
instructions into a sequence of SIMDM instructions in cases where the
hardware doesn't support the original execution size natively for some
particular instruction. The most important use-cases are:
- Lowering send message instructions that don't support SIMD16
natively into SIMD8 (several texturing, framebuffer write and typed
surface operations).
- Lowering messages that don't support SIMD8 natively into SIMD16
(*cough*gen4*cough*).
- 64-bit precision operations (e.g. FP64 and 64-bit integer
multiplication).
- SIMD32.
The algorithm works by splitting the sources of the original
instruction into chunks of width appropriate for the lowered
instructions, and then interleaving the results component-wise into
the destination of the original instruction. The pass is controlled
by the get_lowered_simd_width() function that currently just returns
the original execution size making the whole pass a no-op for the
moment until some user is introduced.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
v2: Reverse order of the source transformations and split_inst emit
call to make the code a bit easier to understand.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=86ae788baefefdb2fa77fe3c242ad2d81c8e834e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 16 15:58:56 2015 +0300
i965/fs: Fix return value of fs_inst::regs_read() for BAD_FILE.
Typically BAD_FILE sources are used to mark a source as not present
what implies that no registers are read. This will become much more
frequent with logical send opcodes which have a large number of
sources, many of them optionally used and marked as BAD_FILE when they
aren't applicable. It will prove to be useful to be able to rely on
the value of regs_read() regardless of whether a source is present or
not.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a5607a16ce7bf5eace2cf4b267af304aef05e90
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 14 19:32:03 2015 +0300
i965/fs: Add builder emit method taking a variable number of source registers.
And start using it in fs_builder::LOAD_PAYLOAD(). This will be used
to emit logical send message opcodes which have an unusually large
number of arguments.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dd3543ac1bebe089bfe3a8ae5efbe3f564e1144
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 17:44:58 2015 +0300
i965/fs: Add stub lowering pass for logical send-message opcodes.
This pass will house ad-hoc lowering code for several send
message-like virtual opcodes that will represent their logically
independent arguments as separate instruction sources rather than as a
single payload blob. This pass will basically just take the separate
arguments that are supposed to be part of the payload and concatenate
them to construct a message in the form required by the hardware.
Virtual instructions in separate-source form will eventually allow
some simplification of the visitor code and make several
transformations easier like lowering SIMD16 instructions to SIMD8
algorithmically in cases where the hardware doesn't support the former
natively.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb7eba97d7235d49ac712a21fb51009c86f3bc64
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 21 17:28:39 2015 +0300
i965/fs: Factor out source components calculation to a separate method.
This cleans up fs_inst::regs_read() slightly by disentangling the
calculation of "components" from the handling of message payload
arguments. This will also simplify the SIMD lowering and logical send
message lowering passes, because it will avoid expressions like
'regs_read * REG_SIZE / component_size' which are not only ugly, they
may be inaccurate because regs_read rounds up the result to the
closest register multiple so they could give incorrect results when
the component size is lower than one register (e.g. uniforms). This
didn't seem to be a problem right now because all such expressions
happen to be dealing with per-channel GRFs only currently, but that's
by no means obvious so better be safe than sorry.
v2: Split PIXEL_X/Y and LINTERP into separate case blocks.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24d74b66883da1955f8c2223367d41470d99df6d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 28 12:07:56 2015 +0300
i965/fs: Simplify instruction rewrite loop in the register coalesce pass.
For some reason the loop that rewrites all occurrences of the
coalesced register was iterating over all possible offsets until it
would find one that compares equal to the offset of a source or
destination of any instruction in the program. Since the mapping
between old and new offsets is already available in the regs_to_offset
array and we know that the whole register has been coalesced we can
just look it up.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=170200e0fcb0b16d20bff86e1258e0a1b2034c10
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 14:20:32 2015 +0300
i965/fs: Fix rewrite of the second half of 16-wide coalesced registers.
The register coalesce pass wasn't rewriting the destination and
sources of instructions that accessed the second half of a coalesced
register previously copied with a 16-wide MOV instruction. E.g.:
| ADD (16) vgrf0:f, vgrf0:f, 1.0:f
| MOV (16) vgrf1:f, vgrf0:f
| MOV (8) vgrf2:f, vgrf0+1:f { sechalf }
would get incorrectly register-coalesced into:
| ADD (16) vgrf1:f, vgrf1:f, 1.0:f
| MOV (8) vgrf2:f, vgrf0+1:f { sechalf }
The reason is that the mov[i] pointer was being left equal to NULL for
every other register. The fact that we've made it to the rewrite loop
implies that the whole register will be coalesced, so it doesn't seem
right not to update something that uses it depending on whether mov[i]
is NULL or not. Fixes an amount of texturing and image_load_store
piglit tests on my SIMD-lowering branch.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0a42b457fb905ce2cc12bb05110ef63656221c9
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 28 11:25:59 2015 +0300
i965/fs: Detect multi-register MOVs correctly in register_coalesce.
register_coalesce() was considering the exec_size of the MOV
instruction alone to decide whether the register at offset+1 of the
source VGRF was being copied to inst->dst.reg_offset+1 of the
destination VGRF, which is only a valid assumption if the move has a
32-bit execution type. Use regs_read() instead to find out the number
of registers copied by the instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
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