Mesa (master): i965: Drop "Vector Mask Enable" bit from 3DSTATE_GS on Gen8+.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 9945573d65f4f66d127df7cbb62648889d09a7ed
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9945573d65f4f66d127df7cbb62648889d09a7ed

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Sun May 10 23:33:30 2015 -0700

i965: Drop "Vector Mask Enable" bit from 3DSTATE_GS on Gen8+.

The documentation makes it pretty clear that we shouldn't use this:

   "Under normal conditions SW shall specify DMask, as the GS stage
    will provide a Dispatch Mask appropriate to SIMD4x2 or SIMD8 thread
    execution (as a function of dispatch mode).  E.g., for SIMD4x2
    execution, the GS stage will generate a Dispatch Mask that is equal
    to what the EU would use as the Vector Mask.  For SIMD8 execution
    there is no known usage model for use of Vector Mask (as there is
    for PS shaders)."

I also managed to find descriptions of DMask and VMask, in the "State
Register" (sr0.2/3) field descriptions:

   "Dispatch Mask (DMask).  This 32-bit field specifies which channels
    are active at Dispatch time."

   "Vector Mask (VMask).  This 32-bit field contains, for each 4-bit
    group, the OR of the corresponding 4-bit group in the dispatch
    mask."

SIMD4x2 shaders process one or two vec4 values, with each 4-bit group
corresponding to xyzw channel enables (either all on, or all off).
Thus, DMask = VMask in SIMD4x2 mode.  But in SIMD8 mode, 4-bit groups
are meaningless, so it just messes up your values.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

---

 src/mesa/drivers/dri/i965/gen8_gs_state.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index 6a0e215..0763e91 100644
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -48,8 +48,7 @@ gen8_upload_gs_state(struct brw_context *brw)
       OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
       OUT_BATCH(stage_state->prog_offset);
       OUT_BATCH(0);
-      OUT_BATCH(GEN6_GS_VECTOR_MASK_ENABLE |
-                brw->geometry_program->VerticesIn |
+      OUT_BATCH(brw->geometry_program->VerticesIn |
                 ((ALIGN(stage_state->sampler_count, 4)/4) <<
                  GEN6_GS_SAMPLER_COUNT_SHIFT) |
                 ((prog_data->base.binding_table.size_bytes / 4) <<