Mesa (master): i965: Use UW-typed immediate in multiply inst.

[Matt Turner]

Module: Mesa
Branch: master
Commit: d46d04529b9c1e55b4c3b65a7078bbbd7ab1a810
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d46d04529b9c1e55b4c3b65a7078bbbd7ab1a810

Author: Matt Turner <mattst88 at gmail.com>
Date:   Tue Jun  2 17:46:38 2015 -0700

i965: Use UW-typed immediate in multiply inst.

Some hardware reads only the low 16-bits even if the type is UD, but
other hardware like Cherryview can't handle this.

Fixes spec at arb_gpu_shader5@execution at sampler_array_indexing@fs-simple on
Cherryview.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90830
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |    2 +-
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 40a3db3..ff05b2a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -788,7 +788,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
       brw_set_default_access_mode(p, BRW_ALIGN_1);
 
       /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
-      brw_MUL(p, addr, sampler_reg, brw_imm_ud(0x101));
+      brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
       if (base_binding_table_index)
          brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
       brw_AND(p, addr, addr, brw_imm_ud(0xfff));
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index ead620b..67495d2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -407,7 +407,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       brw_set_default_access_mode(p, BRW_ALIGN_1);
 
       /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
-      brw_MUL(p, addr, sampler_reg, brw_imm_ud(0x101));
+      brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
       if (base_binding_table_index)
          brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
       brw_AND(p, addr, addr, brw_imm_ud(0xfff));