Mesa (master): i965/gen9: Set HALIGN_16 for all aux buffers

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: a2421623db9b900d2ab0026539e8f7f6294475ea
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2421623db9b900d2ab0026539e8f7f6294475ea

Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Fri May 22 15:57:37 2015 -0700

i965/gen9: Set HALIGN_16 for all aux buffers

Just like the previous patch, but for the GEN9 constraints.

v2:
bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address
this, move the check to where the gen8 check is, and do the appropriate
conditional there.

v3:
Remove stray whitespace introduced in v2 (Chad)
Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part
about gen7 (Chad).

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com> (v1)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com> (v1)
Reviewed-by: Chad Versace <chad.versace at intel.com>

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |   22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f218a2a..8addcc5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -489,10 +489,26 @@ intel_miptree_create_layout(struct brw_context *brw,
    if (layout_flags & MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD)
       mt->array_layout = ALL_SLICES_AT_EACH_LOD;
 
-   /* Use HALIGN_16 if MCS is enabled for non-MSRT */
-   if (brw->gen >= 8 && num_samples < 2 &&
-       intel_miptree_is_fast_clear_capable(brw, mt))
+   /*
+    * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
+    * multisampled or have an AUX buffer attached to it.
+    *
+    * GEN  |    MSRT        | AUX_CCS_* or AUX_MCS
+    *  -------------------------------------------
+    *  9   |  HALIGN_16     |    HALIGN_16
+    *  8   |  HALIGN_ANY    |    HALIGN_16
+    *  7   |      ?         |        ?
+    *  6   |      ?         |        ?
+    */
+   if (intel_miptree_is_fast_clear_capable(brw, mt)) {
+      if (brw->gen >= 9 || (brw->gen == 8 && num_samples == 1))
+         layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+   } else if (brw->gen >= 9 && num_samples > 1) {
       layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+   } else {
+      /* For now, nothing else has this requirement */
+      assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
+   }
 
    brw_miptree_layout(brw, mt, requested, layout_flags);