Mesa (master): i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa ()

[Anuj Phogat]

Module: Mesa
Branch: master
Commit: 278460279b4e089d51a24fb01dc56dc1e88dcb72
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=278460279b4e089d51a24fb01dc56dc1e88dcb72

Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Mon May  4 23:10:28 2015 -0700

i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()

We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8addcc5..593bb9d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2630,7 +2630,9 @@ intel_miptree_map(struct brw_context *brw,
    } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
       intel_miptree_map_blit(brw, mt, map, level, slice);
 #if defined(USE_SSE41)
-   } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) {
+   } else if (!(mode & GL_MAP_WRITE_BIT) &&
+              !mt->compressed && cpu_has_sse4_1 &&
+              (mt->pitch % 16 == 0)) {
       intel_miptree_map_movntdqa(brw, mt, map, level, slice);
 #endif
    } else {