Mesa (master): i965/gen9: Disable Mip Tail for YF/YS tiled surfaces

[Anuj Phogat]

Module: Mesa
Branch: master
Commit: e20345204d8fe8864240be2428ac0f225b92b7cc
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e20345204d8fe8864240be2428ac0f225b92b7cc

Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Tue Apr 14 22:06:50 2015 -0700

i965/gen9: Disable Mip Tail for YF/YS tiled surfaces

Disabling miptails fixed the buffer corruption happening in FBO
which use YF/YS tiled renderbuffer or texture as color attachment.

Spec recommends disabling mip tails only for non-mip-mapped surfaces.
But, without disabling miptails I couldn't get correct data out of
mipmapped YF/YS tiled surface.

We need better understanding of miptails before start using them.
For now this patch helps move things forward.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

---

 src/mesa/drivers/dri/i965/brw_defines.h        |    3 +++
 src/mesa/drivers/dri/i965/gen8_surface_state.c |   10 ++++++++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 54e5a8f..bfcc442 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -598,6 +598,9 @@
 #define GEN9_SURFACE_TRMODE_TILEYF         1
 #define GEN9_SURFACE_TRMODE_TILEYS         2
 
+#define GEN9_SURFACE_MIP_TAIL_START_LOD_SHIFT      8
+#define GEN9_SURFACE_MIP_TAIL_START_LOD_MASK       INTEL_MASK(11, 8)
+
 /* Surface state DW6 */
 #define GEN7_SURFACE_MCS_ENABLE                 (1 << 0)
 #define GEN7_SURFACE_MCS_PITCH_SHIFT            3
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 2514d96..b2d1a57 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -255,8 +255,11 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
    surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
              (max_level - min_level - 1); /* mip count */
 
-   if (brw->gen >= 9)
+   if (brw->gen >= 9) {
       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
+      /* Disable Mip Tail by setting a large value. */
+      surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
+   }
 
    if (aux_mt) {
       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
@@ -478,8 +481,11 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
 
    surf[5] = irb->mt_level - irb->mt->first_level;
 
-   if (brw->gen >= 9)
+   if (brw->gen >= 9) {
       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
+      /* Disable Mip Tail by setting a large value. */
+      surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
+   }
 
    if (aux_mt) {
       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |