Mesa (amdgpu): winsys/amdgpu: sync buffer accesses to different rings

[Marek Olšák]

Module: Mesa
Branch: amdgpu
Commit: 5ba350b05923ea83a831fd94e6020c7ecf667ad6
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ba350b05923ea83a831fd94e6020c7ecf667ad6

Author: Christian König <christian.koenig at amd.com>
Date:   Mon Jun 15 20:05:48 2015 +0200

winsys/amdgpu: sync buffer accesses to different rings

Without the GPU scheduler the kernel won't sync the access for
us any more. So do so manually in the amdgpu winsys.

Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by Leo Liu <leo.liu at amd.com>

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 8aafc45..a4edb08 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -469,6 +469,19 @@ void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs, struct amdgpu_cs_context
    int i, r;
    uint64_t fence;
 
+   for (i = 0; i < csc->num_buffers; i++) {
+      struct amdgpu_fence *bo_fence = (void *)csc->buffers[i].bo->fence;
+      if (!bo_fence)
+         continue;
+
+      if (bo_fence->ctx == cs->ctx &&
+          bo_fence->ip_type == cs->cst->request.ip_type &&
+          bo_fence->ring == cs->cst->request.ring)
+         continue;
+
+      amdgpu_fence_wait(&cs->ctx->ws->base, (void *)bo_fence, PIPE_TIMEOUT_INFINITE);
+   }
+
    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &csc->request, 1, &fence);
    if (r) {
       fprintf(stderr, "amdgpu: The CS has been rejected, "