Mesa (master): i965/fs: Don' t mess up stride for uniform integer multiplication.

[Matt Turner]

Module: Mesa
Branch: master
Commit: a49328d58d1e3e143f9434976d9f3574acefc4ea
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a49328d58d1e3e143f9434976d9f3574acefc4ea

Author: Matt Turner <mattst88 at gmail.com>
Date:   Mon Jun 22 10:59:33 2015 -0700

i965/fs: Don't mess up stride for uniform integer multiplication.

If the stride is 0, the source is a uniform and we should not modify the
stride.

Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91047
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |   20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5563c5a..903624c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3196,10 +3196,16 @@ fs_visitor::lower_integer_multiplication()
                src1_1_w.fixed_hw_reg.dw1.ud >>= 16;
             } else {
                src1_0_w.type = BRW_REGISTER_TYPE_UW;
-               src1_0_w.stride = 2;
+               if (src1_0_w.stride != 0) {
+                  assert(src1_0_w.stride == 1);
+                  src1_0_w.stride = 2;
+               }
 
                src1_1_w.type = BRW_REGISTER_TYPE_UW;
-               src1_1_w.stride = 2;
+               if (src1_1_w.stride != 0) {
+                  assert(src1_1_w.stride == 1);
+                  src1_1_w.stride = 2;
+               }
                src1_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
             }
             ibld.MUL(low, inst->src[0], src1_0_w);
@@ -3209,10 +3215,16 @@ fs_visitor::lower_integer_multiplication()
             fs_reg src0_1_w = inst->src[0];
 
             src0_0_w.type = BRW_REGISTER_TYPE_UW;
-            src0_0_w.stride = 2;
+            if (src0_0_w.stride != 0) {
+               assert(src0_0_w.stride == 1);
+               src0_0_w.stride = 2;
+            }
 
             src0_1_w.type = BRW_REGISTER_TYPE_UW;
-            src0_1_w.stride = 2;
+            if (src0_1_w.stride != 0) {
+               assert(src0_1_w.stride == 1);
+               src0_1_w.stride = 2;
+            }
             src0_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
 
             ibld.MUL(low, src0_0_w, inst->src[1]);