Mesa (master): i965/fs: set execution size to 8 with simd8 ddy instruction

[Tapani Pälli]

Module: Mesa
Branch: master
Commit: 58715b72396133350c1549381553121f936a198e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=58715b72396133350c1549381553121f936a198e

Author: Tapani Pälli <tapani.palli at intel.com>
Date:   Tue May 12 14:24:08 2015 +0300

i965/fs: set execution size to 8 with simd8 ddy instruction

Commit dd5c825 changed the way how execution size for instructions
get set. Previously it was based on destination register width, now
it is set explicitly when emitting instructions.

Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90258

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |    1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index a99b7f7..b6b0d05 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -941,6 +941,7 @@ fs_generator::generate_ddy(enum opcode opcode,
       brw_push_insn_state(p);
       brw_set_default_access_mode(p, BRW_ALIGN_16);
       if (unroll_to_simd8) {
+         brw_set_default_exec_size(p, BRW_EXECUTE_8);
          brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
          if (negate_value) {
             brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));