Mesa (master): i965/fs: Rework compression control selection.

[Matt Turner]

Module: Mesa
Branch: master
Commit: 0a9e3a0160bbda8ea23aeb049f9c3dfc0478bbf5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a9e3a0160bbda8ea23aeb049f9c3dfc0478bbf5

Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu May 14 15:58:20 2015 -0700

i965/fs: Rework compression control selection.

The next commit uses an add(16) with a UW destination with a stride of
2, which needs compression control since it's writing two registers. The
old code would have failed to set compression control correctly.

Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index b6b0d05..0be0f86 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1601,10 +1601,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
          break;
       case 16:
       case 32:
-         if (type_sz(inst->dst.type) < sizeof(float))
-            brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
-         else
+         /* If the instruction writes to more than one register, it needs to
+          * be a "compressed" instruction on Gen <= 5.
+          */
+         if (inst->exec_size * inst->dst.stride * type_sz(inst->dst.type) > 32)
             brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+         else
+            brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
          break;
       default:
          unreachable("Invalid instruction width");