[Mesa-dev] [PATCH 12/13] i915g: implement unfenced color&depth buffer using tiling bits

[Chris Wilson]

On Sat, 20 Nov 2010 22:43:56 +0100, Jakob Bornecrantz <wallbraker at gmail.com> wrote:
> On Fri, Nov 19, 2010 at 11:38 PM, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > Â #define BUF_3D_TILED_SURFACE Â  (1<<22)
> > Â #define BUF_3D_TILE_WALK_X Â  Â  0
> > Â #define BUF_3D_TILE_WALK_Y Â  Â  (1<<21)
> > +#define BUF_3D_TILE_BITS(tiling) (((tiling) ? BUF_3D_TILED_SURFACE : 0) \
> > + Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  | ((tiling) == I915_TILE_Y ? Â BUF_3D_TILE_WALK_Y : 0))
> 
> Hmm are textures never X tiled?

The macro is correct if rather obtuse. I prefer

static inline uint32_t i915_buf_tiling(uint32_t tiling)
{
        uint32_t v = 0;
        switch (tiling) {
        case I915_TILING_Y: v |= BUF_3D_TILE_WALK_Y;
        case I915_TILING_X: v |= BUF_3D_TILED_SURFACE;
        case I915_TILING_NONE: break;
        }
        return v;
}

-- 
Chris Wilson, Intel Open Source Technology Centre